ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 12
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
7.4
Figure 7-2.
7.4.1
7.4.2
8135J–AVR–12/10
Byte Address
Data Memory
I/O Memory
SRAM Data Memory
2FFF
17FF
1000
2000
FFF
Data Memory Map (Hexadecimal address)
0
ATxmega64D4
Internal SRAM
I/O Registers
RESERVED
EEPROM
(4 KB)
(4KB)
(2K)
The Data Memory containts the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see
devices in the family is identical and with empty, reserved memory space for smaller devices.
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the
eral Module Address Map” on page
The XMEGA D4 devices have internal SRAM memory for data storage.
Byte Address
Figure 7-2 on page
2FFF
13FF
1000
2000
FFF
0
50.
ATxmega32D4
Internal SRAM
I/O Registers
RESERVED
EEPROM
(1 KB)
(4 KB)
(4KB)
12. To simplify development, the memory map for all
Byte Address
Byte Address
3FFF
17FF
1000
2000
13FF
27FF
FFF
1000
2000
FFF
0
0
XMEGA D4
ATxmega128D4
Internal SRAM
ATxmega16D4
Internal SRAM
I/O Registers
I/O Registers
RESERVED
EEPROM
RESERVED
EEPROM
(4 KB)
(1 KB)
(2 KB)
(4KB)
(2K)
(8K)
”Periph-
12