ATxmega192A3 Atmel Corporation, ATxmega192A3 Datasheet - Page 57
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ATxmega192A3
Manufacturer Part Number
ATxmega192A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192A3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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5.14.3
8077H–AVR–12/09
ADDRCTRL - DMA Channel Address Control Register
• Bit [3:2] - ERRINTLVL[1:0]: DMA Channel Error Interrupt Level
These bits enable the interrupt for DMA channel transfer error select the interrupt level as
described in
123. The enabled interrupt will trigger for the conditions when the ERRIF is set.
• Bit [1:0] - TRNINTLVL[1:0]: DMA Channel Transaction Complete Interrupt Level
These bits enable the interrupt for DMA channel transaction complete and select the interrupt
level as described in
on page
• Bit 7:6 - SRCRELOAD[1:0]: DMA Channel Source Address Reload
These bits decide the DMA channel source address reload according to
can not be changed if the channel is busy.
Table 5-4.
• Bit 5:4 - SRCDIR[1:0]: DMA Channel Source Address Mode
These bits decide the DMA channel source address mode according to
can not be changed if the channel is busy.
Table 5-5.
• Bit 3:2 - DESTRELOAD[1:0]: DMA Channel Destination Address Reload
These bits decide the DMA channel destination address reload according to
58. These bits can not be changed if the channel is busy.
Bit
+0x02
Read/Write
Initial Value
SRCRELOAD[1:0]
SRCDIR[1:0]
123. The enabled interrupt will trigger for the conditions when the TRNIF is set.
00
01
10
11
00
01
10
11
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
R/W
SRCRELOAD[1:0]
DMA channel source address reload settings
DMA channel source address mode settings
7
0
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller”
Group Configuration
R/W
Group Configuration
6
0
TRANSACTION
BLOCK
BURST
FIXED
NONE
DEC
INC
R/W
-
5
0
SRCDIR[1:0]
R/W
4
0
Description
Fixed
Increment
Decrement
Reserved
Description
No reload performed.
DMA source address register is reloaded with initial
value at end of each block transfer.
DMA source address register is reloaded with initial
value at end of each burst transfer.
DMA source address register is reloaded with initial
value at end of each transaction.
DESTRELOAD[1:0]
3
R
0
R/W
2
0
R/W
1
0
DESTDIR[1:0]
Table
Table
XMEGA A
Table 5-6 on page
R/W
5-5. These bits
0
0
5-4. These bits
ADDRCTRL
57
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