ATxmega192A3 Atmel Corporation, ATxmega192A3 Datasheet - Page 145
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ATxmega192A3
Manufacturer Part Number
ATxmega192A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192A3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.15.4
8077H–AVR–12/09
CLKEVOUT - Clock and Event Out Register
Table 13-6.
• Bit 7:6 - Reserved
These bits are reserved and will always be read as one. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5:4 - EVOUT[1:0] - Event Output Port
These bits decide which port the Event Channel 0 from the Event System should be output to.
Pin 7 on the selected port is always used, and the CLKOUT bits must be set different from
EVOUT. The pin must be configured as an output pin for the Signaling Event to be available on
the pin.
Table 13-7 on page 145
Table 13-7.
• Bits 3:2 - Reserved
These bits are reserved and will always be read as one. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1:0 - CLKOUT[1:0] - Clock Output Port
These bits decide which port the Peripheral Clock should be output to. Pin 7 on the selected port
is always used. The Clock output setting, will override the Event output setting, thus if both are
enabled on the same port pin, the Peripheral Clock will be visible. The pin must be configured as
an output pin for the Clock to be available on the pin.
Table 13-8 on page 146
Bit
+0x04
Read/Write
Initial Value
EVOUT[1:0]
00
01
10
11
VPnMAP[3:0]
1101
1110
1111
R
7
0
-
Virtual Port mapping. (Continued)
Event Channel 0 output configurations
Group Configuration
PORTP
PORTQ
PORTR
6
R
0
-
shows the possible configurations.
shows the possible configurations.
Group Configuration
OFF
PC7
PD7
PE7
R/W
5
0
EVOUT[1:0]
R/W
4
0
Description
Event out disabled
Event Channel 0 output on Port C pin 7
Event Channel 0 output on Port D pin 7
Event Channel 0 output on Port E pin 7
3
R
0
-
Description
PORTP mapped to virtual Port n
PORTQ mapped to virtual Port n
PORTR mapped to virtual Port n
R
2
0
-
R/W
1
0
CLKOUT[1:0]
XMEGA A
R/W
0
0
CLKEVOUT
145
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