ATxmega192A3 Atmel Corporation, ATxmega192A3 Datasheet - Page 117
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ATxmega192A3
Manufacturer Part Number
ATxmega192A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192A3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ATxmega192A3-AU
Manufacturer:
TOSHIBA
Quantity:
1 200
Company:
Part Number:
ATxmega192A3-MH
Manufacturer:
TI/NSC
Quantity:
56
Company:
Part Number:
ATxmega192A3U-AU
Manufacturer:
MSDS
Quantity:
124
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11. WDT – Watchdog Timer
11.1
11.2
11.3
8077H–AVR–12/09
Features
Overview
Normal Mode Operation
•
•
•
•
The Watchdog Timer (WDT) is a system function for monitoring correct program operation, mak-
ing it possible to recover from error situations, for instance run-away code. The WDT is a timer,
configured to a predefined timeout period and is constantly running when enabled. If the WDT is
not reset within the timeout period, it will issue a system reset. The WDT is reset by executing
the WDR (Watchdog Timer Reset) instruction from the application code.
The WDT also has a window mode that enables the user to define a time slot where WDT must
be reset within. If the WDT is reset too early or too late, a system reset will be issued.
The WDT will run in all power modes if enabled. It runs from a CPU independent clock source,
and will continue to operate to issue a system reset even if the main clocks fail.
The Configuration Change Protection mechanism ensures that the WDT settings cannot be
changed by accident. In addition the settings can be locked by a fuse.
In normal mode operation a single timeout period is set for the WDT. If the WDT is not reset from
the application code before the timeout occurs the WDT will issue a system reset. There are 11
possible WDT timeout (TO
any time during the period. After each reset, a new timeout period is started. The default timeout
period is controlled by fuses. Normal mode operation is illustrated in
Figure 11-1. Normal mode operation.
11 selectable timeout period, from 8 ms to 8s
Two operation modes
Runs from 1 kHz Ultra Low Power clock reference
Configuration lock
– Standard mode
– Window mode
TO
WDT
= 16
WDT Count
WDT
5
) periods selectable from 8 ms to 8s, and the WDT can be reset at
10
15
System Reset
20
Timely WDT
Reset
TO
25
WDT
30
Figure
35
WDT Timeout
11-1.
XMEGA A
t [ms]
117
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