ATxmega128A1 Atmel Corporation, ATxmega128A1 Datasheet - Page 9

• Manufacturer Part Number: ATxmega128A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.3
6.4
6.5
8067M–AVR–09/10
Register File
ALU - Arithmetic Logic Unit
Program Flow
concept enables instructions to be executed in every clock cycle. The program memory is In-
System Self-Programmable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU cycle, the operation is performed on two Register File operands, and the result is stored
back in the Register File.
Six of the 32 registers can be used as three 16-bit address register pointers for data space
addressing - enabling efficient address calculations. One of these address pointers can also be
used as an address pointer for look up tables in Flash program memory.
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient
implementation of 32-bit aritmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
XMEGA A1
9