ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 79
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
10.2.2
10.2.3
32142AS–12/2011
WDT
SPI
1. WDT Control Register does not have synchronization feedback
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
2. Disabling SPI has no effect on the SR.TDRE bit
3. SPI disable does not work in SLAVE mode
4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
5. SPI mode fault detection enable causes incorrect behavior
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-
tion in the SCIF memory range.
Fix/Workaround
None.
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
ATUC64/128/256L3/4U
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