ATtiny88 Automotive Atmel Corporation, ATtiny88 Automotive Datasheet - Page 26

• Manufacturer Part Number: ATtiny88 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny88 Automotive

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6. System Clock and Clock Options
6.1
6.1.1
6.1.2
6.1.3
26
Clock Systems and their Distribution
ATtiny88 Automotive
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 6-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 6-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules such as Timer/Counters, the Serial
Peripheral Interface and the External Interrupt module. Note, that some external interrupts are
detected by asynchronous logic, meaning they are recognized even if the I/O clock is halted.
Also note that the start condition detection of the Two-Wire Interface module is asynchronous,
meaning TWI address recognition works in all sleep modes (even when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
FLASH
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
clk
TWI
TWIHS
EXTERNAL
CLOCK
PRESCALER
SWITCH
CLOCK
CLOCK
I/O MODULES
clk
GENERAL
SOURCE CLOCK
I/O
34. The clock systems are detailed below.
CLOCK CONTROL UNIT
OSCILLATOR
WATCHDOG
ADC
RESET
LOGIC
clk
ADC
WATCHDOG
CLOCK
CORE
CPU
clk
RAM
CPU
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
FLASH AND
EEPROM
clk
FLASH
I/O
is halted).
“Power Manage-
9157B–AVR–01/10