ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet
ATTINY88-15MZ
Specifications of ATTINY88-15MZ
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ATTINY88-15MZ Summary of contents
Page 1
... General Purpose Working Registers – Fully Static Operation • High Endurance Non-volatile Memory Segments – 8K Bytes of In-System Self-Programmable Flash program memory(ATtiny88) – 64 Bytes EEPROM – 512 Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Programming Lock for Software Security • ...
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... Disclaimer Typical values contained in this data sheet are based on simulations and characterization of actual ATtiny88 AVR microcontrollers manufactured on the typical process technology. Applica- ble Automotive Min. and Max. values are based on characterization of devices representative of the whole process excursion (corner run). ATtiny88 Automotive 2 9157B– ...
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... The various special features of Port C are elaborated in 68. 9157B–AVR–01/10 “System Clock and Clock Options” on page Table 21-4 on page ATtiny88 Automotive “Alternate Functions of Port B” on page 26. 211. Shorter pulses are not guaranteed to “Alternate Functions of Port C” on page 3 ...
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... V Canceling Techniques” on page The following pins receive their supply voltage from AV ages) PA1:0. All other I/O pins take their supply voltage from V ATtiny88 Automotive 4 “Alternate Functions of Port D” on page even if the ADC is not used. If the ADC is used recom- ...
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... Overview The ATtiny88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Self-Programmable Flash on a monolithic chip, the Atmel ATtiny88 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny88 AVR is supported by a full suite of program and system development tools includ- ing: C compilers, macro assemblers, program debugger/simulators and evaluation kits. ...
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... Disclaimer Typical values contained in this data sheet are based on simulations and characterization of actual ATtiny88 AVR microcontrollers manufactured on the typical process technology. Applica- ble Automotive Min. and Max. values are based on characterization of devices representative of the whole process excursion (corner run). 9157B–AVR–01/10 ...
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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATtiny88 Automotive 8 Block Diagram of the AVR Architecture ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 – 0x5F. In addition, the ATtiny88 has Extended I/O space from 0x60 – 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATtiny88 Automotive ...
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... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4-2, each register is also assigned a data memory address, mapping them ATtiny88 Automotive 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/Write Initial Value ATtiny88 Automotive 12 The X-, Y-, and Z-registers R27 (0x1B) ...
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... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. ATtiny88 Automotive “Memory Programming” ...
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... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ ATtiny88 Automotive 14 “Interrupts” on page 48 for more information. ; store SREG value ; disable interrupts during timed sequence ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 9157B–AVR–01/10 ; set Global Interrupt Enable ATtiny88 Automotive 15 ...
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... SPM instruction can be executed from the entire Flash. See SELFPRGEN description in section “SPMCSR – Store Program Memory Control and Status Register” on page 189 The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny88 Pro- gram Counter (PC) is 11/12 bits wide, thus addressing the 4K program memory locations. ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the ATtiny88 are all accessible through all these addressing modes. The Register File is described in 11 ...
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... EEPROM Data Memory ATtiny88 devices contain 64 bytes of data EEPROM memory, organized as a separate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Figure 5-1 on page 23. The EEPE bit remains set until the erase Figure 5-1 on page 23). The EEPE bit remains set until the erase operation “OSCCAL – Oscillator Calibration Register” on ATtiny88 Automotive Figure 5-1 on page 23). The EEPE bit 19 ...
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... Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData ATtiny88 Automotive 20 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r17) in address register out EEARL, r17 ; Write data (r19) to Data Register out EEDR,r19 ; Write logical one to EEMPE sbi EECR,EEMPE ...
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... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is too CC reset Protection circuit can be used reset occurs while a write CC ATtiny88 Automotive 21 ...
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... I/O Memory The I/O space definition of the ATtiny88 is shown in All ATtiny88 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 – ...
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... R R R/W R EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use ATtiny88 Automotive LSB R/W R/W R/W R EERIE EEMPE EEPE EERE R/W R/W R/W ...
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... The user should poll the EEPE bit before starting the read operation write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. ATtiny88 Automotive 24 Table 5-2 lists the typical pro- ...
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... EEPROM Programming Time Number of Calibrated Oscillator Cycles 26,368 MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATtiny88 Automotive Typ Programming Time 3 LSB R/W R/W R/W R LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR2 ...
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... FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. ATtiny88 Automotive 26 presents the principal clock systems in the AVR and their distribution. All of the clocks 34. The clock systems are detailed below. ...
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... CC , the device issues an internal reset with a time-out delay (t CC Table 6-2. The frequency of the Watchdog oscillator is voltage ATtiny88 Automotive “System Control and Reset” on page timed from the Watchdog TOUT “Internal Oscillator Speed” on page 228 228. ...
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... The accuracy of this calibration is shown as User calibration in When this oscillator is used as the chip clock, the Watchdog oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali- bration value, see the section ATtiny88 Automotive 28 Length of Startup Sequence. SUT1:0 ...
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... Start-up Times for the 128 kHz Internal Oscillator Power Conditions BOD enabled Fast rising power Slowly rising power 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + ensure programming mode can be entered. ATtiny88 Automotive (1)(2) Nominal Frequency (MHz) 8.0 Start-up Time Additional Delay from Power-down ...
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... MCU is kept in Reset during the changes. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to 31 for details. ATtiny88 Automotive 30 30. To run the device on an external clock, the CKSEL Fuses must be programmed to Table 6-7). ...
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... System Clock Prescaler The ATtiny88 has a system clock prescaler, and the system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page tem clock frequency and the power consumption when the requirement for processing power is low ...
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... The division factors are given in Table 6-9. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to 0b0000. If CKDIV8 is programmed, CLKPS bits are reset to 0b0011, giving a division factor start up. ATtiny88 Automotive ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 6-9. CLKPS3 9157B–AVR–01/10 Clock Prescaler Select CLKPS2 CLKPS1 ATtiny88 Automotive CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 33 ...
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... MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 49 ATtiny88 Automotive 34 for more details. presents the different clock systems in the ATtiny88, and their distribu- Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domain X 1. For INT1 and INT0, only level interrupt for a summary ...
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... CPU FLASH , clk , and clk , while allowing the other clocks to run. I/O CPU FLASH “Clock Sources” on page ATtiny88 Automotive “External Interrupts” on page 49 27. Table 20-4 on page level has CC 35 ...
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... If the reference is kept on in sleep mode, the output can be used immediately. Refer to age Reference” on page 43 ATtiny88 Automotive 36 38. Writing this bit to one turns off the BOD in 38. ...
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... Digital CC “DIDR1 – Digital Input Disable Register 1” on page 163 for details – – – – ATtiny88 Automotive ) are stopped, the input buffers of the device will and “DIDR0 – Digital – SM1 SM0 SE R R/W R/W R Table 7-2. ...
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... Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. ATtiny88 Automotive 38 Sleep Mode Select SM0 ...
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... Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot be used when the ADC is shut down. 9157B–AVR–01/ PRTWI – PRTIM0 – R ATtiny88 Automotive PRTIM1 PRSPI – PRADC R/W R PRR 39 ...
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... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in ATtiny88 Automotive 40 Figure 8-1 shows the reset circuit ...
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... Reset Sources The ATtiny88 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the required pulse length. ...
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... Figure 8-4. 8.2.3 Brown-out Detection ATtiny88 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny88 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to The Wathdog Timer can also be configured to generate an interrupt instead of a reset ...
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... WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleare d. The value written to the WDE bit is irrelevant. ATtiny88 Automotive 44 WDT Configuration as a Function of the WDTON Fuse Setting ...
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... Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. 9157B–AVR–01/ – – – – WDIF WDIE WDP3 WDCE R/W R/W R/W R ATtiny88 Automotive WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description WDE WDP2 WDP1 WDP0 R/W R/W R/W R MCUSR WDTCSR 45 ...
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... Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler Bits and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 8-3 on page ATtiny88 Automotive 46 Watchdog Timer Configuration WDE ...
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... If selected, one of the valid settings below 0b1010 will be used. ATtiny88 Automotive Number of Typical Time-out at WDT Oscillator Cycles 2K (2048) cycles 4K (4096) cycles 8K (8192) cycles 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles ...
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... Interrupts This section describes the specifics of interrupt handling in ATtiny88. For a general explanation of the AVR interrupt handling, refer to 9.1 Interrupt Vectors Table 9-1. Vector No The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny88 is: Address Labels Code ...
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... SPL,r16 sei <inst> xxx ... ... ... “EICRA – External Interrupt Control Register A” on page 26. ATtiny88 Automotive ; Watchdog Timer Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler ; Timer0 Compare A Handler ; Timer0 Compare B Handler ; Timer0 Overflow Handler ; SPI Transfer Complete Handler ...
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... SLEEP command. 9.2.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag ATtiny88 Automotive 50 Timing of pin change interrupts pin_lat D Q pin_sync LE clk PCINT(0) in PCMSK(x) clk PCIF 26. ...
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... Interrupt 0 Sense Control ISC00 Description 0 The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request. ATtiny88 Automotive ISC11 ISC10 ISC01 ISC00 R/W R/W ...
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... Initial Value • Bits 7..2 – Res: Reserved Bits These bits are unused in ATtiny88, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 9157B–AVR–01/ – – – – – – – – ATtiny88 Automotive PCIE3 PCIE2 PCIE1 PCIE0 R/W R/W R/W R PCIF3 PCIF2 PCIF1 PCIF0 R/W R/W R/W R PCICR PCIFR ...
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... Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny88 Automotive ...
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... I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9157B–AVR–01/ PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATtiny88 Automotive PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK1 PCMSK0 ...
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... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny88 Automotive 56 and Ground as indicated in CC for a complete list of parameters. ...
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... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 73, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATtiny88 Automotive Figure 10-2 shows a func- ...
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... Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11 intermediate step. ATtiny88 Automotive 58 R16 R17 out DDRx, r16 ...
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... PINxn Register bit and the preceding latch con- SYSTEM CLK XXX SYNC LATCH PINxn r17 Figure 10-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of ATtiny88 Automotive Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) ...
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... The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example Note: ATtiny88 Automotive 60 SYSTEM CLK r16 out PORTx, r16 ...
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... Read port pins */ i = PINB; ... Figure 10-2, the digital input signal can be clamped to ground at the input of the / GND is not recommended, since this may cause excessive currents if the pin is CC ATtiny88 Automotive “Alternate Port Functions” on page Figure 10-2 can be overridden by 61. Figure 10-6 61 ...
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... Figure 10-6. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATtiny88 Automotive 62 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used Input/Output bi-directionally. ATtiny88 Automotive Fig- 63 ...
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... Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATtiny88 Automotive 64 Port A Pins Alternate Functions Alternate Function PA3 PCINT27 (Pin Change Interrupt 27) PA2 PCINT26 (Pin Change Interrupt 26) ADC7 (ADC Input Channel 7) PA1 PCINT25 (Pin Change Interrupt 25) ADC6 (ADC Input Channel 6) ...
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... SS (SPI Bus Master Slave select) OC1B (Timer/Counter1 Output Compare Match B Output) PCINT2 (Pin Change Interrupt 2) OC1A (Timer/Counter1 Output Compare Match A Output) PCINT1 (Pin Change Interrupt 1) ICP1 (Timer/Counter1 Input Capture Input) CLKO (Divided System Clock Output) PCINT0 (Pin Change Interrupt 0) ATtiny88 Automotive Table 10-5. 65 ...
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... PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source. Table 10-6 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATtiny88 Automotive 66 and Table 10-7 relate the alternate functions of Port B to the overriding signals Figure 10-6 on page 62 ...
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... PCINT3 • PCIE0 PCINT2 • PCIE0 1 1 PCINT3 INPUT PCINT2 INPUT SPI SLAVE INPUT SPI SS – – ATtiny88 Automotive PB5/SCK/ PB4/MISO/ PCINT5 PCINT4 SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR ...
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... PC5 can also be used as ADC input Channel 5. Note that ADC input chan- nel 5 uses digital power. PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt source. ATtiny88 Automotive 68 Port C Pins Alternate Functions Alternate Function PC7 ...
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... PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source. 9157B–AVR–01/10 ATtiny88 Automotive 69 ...
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... Table 10-10. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATtiny88 Automotive 70 and Table 10-10 relate the alternate functions of Port C to the overriding signals Figure 10-6 on page 62. Overriding Signals for Alternate Functions in PC6..PC4 PC6/RESET/ PC7/PCINT15 PCINT14 0 RSTDISBL ...
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... T0 (Timer/Counter 0 External Counter Input) PD4 PCINT20 (Pin Change Interrupt 20) INT1 (External Interrupt 1 Input) PD3 PCINT19 (Pin Change Interrupt 19) INT0 (External Interrupt 0 Input) PD2 PCINT18 (Pin Change Interrupt 18) PD1 PCINT17 (Pin Change Interrupt 17) PD0 PCINT16 (Pin Change Interrupt 16) ATtiny88 Automotive Table 10-11. 71 ...
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... Table 10-12 shown in Table 10-12. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATtiny88 Automotive 72 and Table 10-13 relate the alternate functions of Port D to the overriding signals Figure 10-6 on page 62. PD7/AIN1/PCINT23 PD6/AIN0/PCINT22 ...
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... BPDS BPDSE PUD R R/W R for more details about this feature BBMD BBMC BBMB BBMA R/W R/W R “Break-Before-Make Switching” on page ATtiny88 Automotive PD1/PCINT17 PD0/PCINT16 PCINT17 • PCIE2 PCINT16 • PCIE2 1 1 PCINT17 INPUT PCINT16 INPUT – – – – ...
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... PORTB – The Port B Data Register Bit Read/Write Initial Value 10.4.7 DDRB – The Port B Data Direction Register Bit Read/Write Initial Value 10.4.8 PINB – The Port B Input Pins Bit Read/Write Initial Value ATtiny88 Automotive 74 “Configuring the Pin” on page ...
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... PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATtiny88 Automotive PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 R R ...
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... Timer/Counter Register Description” on page The PRTIM0 bit in enable Timer/Counter0 module. Figure 11-1. 8-bit Timer/Counter Block Diagram ATtiny88 Automotive 76 “Pinout of ATtiny88” on page 2. CPU accessible I/O Registers, including I/O bits “PRR – Power Reduction Register” on page 38 Count Clear Control Logic ...
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... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. “Timer/Counter0 and Timer/Counter1 Prescalers” on page ATtiny88 Automotive ). T0 116. 77 ...
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... If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe- cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. Figure 11-3 ATtiny88 Automotive 78 DATA BUS count TCNTn clear Increment or decrement TCNT0 by 1 ...
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... TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. 9157B–AVR–01/10 ATtiny88 Automotive DATA BUS OCRnx = (8-bit Comparator ) OCFnx (Int ...
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... Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when interrupt flags are set. shows the count sequence close to the MAX value in all modes. ATtiny88 Automotive Figure 11-5 contains timing data for basic Timer/Counter operation ...
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... I/O MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode where OCR0A ATtiny88 Automotive MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value ...
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... This bit control the counting sequence of the counter, the source for maximum (TOP) counter value, see mode (counter), Clear Timer on Compare Match (CTC) mode (see page 79). Table 11-2. Mode 0 1 Notes: • Bits 2:0 – CS02:0: Clock Select ATtiny88 Automotive 82 caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 7 ...
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... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ATtiny88 Automotive TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R OCR0B[7:0] R/W R/W R TCNT0 ...
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... OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor- responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. ATtiny88 Automotive ...
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... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. See Table 9157B–AVR–01/10 11-2, “CTC Mode Bit Description” on page ATtiny88 Automotive 82. 85 ...
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... TCNT1 for accessing Timer/Counter1 counter value and so on. The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1. 16-bit Timer/Counter Block Diagram Note: ATtiny88 Automotive 86 Figure 12-1. Count Clear ...
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... BOTTOM MAX TOP 9157B–AVR–01/10 “Pinout of ATtiny88” on page “Register Description” on page “PRR – Power Reduction Register” on page 38 94.. The compare match event will also set the Compare Match 160.) The Input Capture unit includes a digital filtering unit (Noise The counter reaches the BOTTOM when it becomes 0x0000 ...
Page 88
... The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples C Code Examples Note: ATtiny88 Automotive 88 (1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATtiny88 Automotive 89 ...
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... If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATtiny88 Automotive 90 (1) ...
Page 91
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ATtiny88 Automotive 116. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...
Page 92
... When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. ATtiny88 Automotive 92 DATA BUS TEMP (8-bit) ...
Page 93
... ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. 9157B–AVR–01/10 88. ATtiny88 Automotive “Accessing 16-bit Registers” (Figure 13-1 on page 116). The edge detector is also ...
Page 94
... Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. ATtiny88 Automotive 94 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “ ...
Page 95
... TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM 88. ATtiny88 Automotive DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 COMnx1:0 “ ...
Page 96
... PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin system reset occur, the OC1x Register is reset to “0”. ATtiny88 Automotive 96 Figure 12-5 shows a simplified ...
Page 97
... For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 9157B–AVR–01/10 Waveform D Generator OCnx D PORT D DDR See “Register Description” on page 108. Table 12-2 on page ATtiny88 Automotive Table 12-2, Table 12-3 and 109. For fast PWM mode refer to OCnx Pin ...
Page 98
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATtiny88 Automotive 98 (See “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page 96.) 106 ...
Page 99
... PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. 9157B–AVR–01/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I ------------------------------------------------------- OCnA 2 ATtiny88 Automotive OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O N OCRnA ...
Page 100
... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. ATtiny88 Automotive 100 log R ...
Page 101
... OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of f similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com- pare unit is enabled in the fast PWM mode. 9157B–AVR–01/10 ATtiny88 Automotive Table on page f clk_I/O f ...
Page 102
... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter- rupt Flag will be set when a compare match occurs. Figure 12-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATtiny88 Automotive 102 TOP log + ...
Page 103
... TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1 the OC1A output will toggle with a 50% duty cycle. 9157B–AVR–01/10 ATtiny88 Automotive Figure 12-8 f clk_I/O f ...
Page 104
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. ATtiny88 Automotive 104 Figure 12-9). ...
Page 105
... The actual OC1x value will only be visible on the port pin if the data direction ATtiny88 Automotive OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 106
... Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx OCFnx Figure 12-11 ATtiny88 Automotive 106 f = OCnxPFCPWM Figure 12-10 OCRnx - 1 OCRnx OCRnx Value shows the same timing data, but with the prescaler enabled. f clk_I/O --------------------------------- ...
Page 107
... TOP in various modes. When using phase and I/O Tn /1) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value shows the same timing data, but with the prescaler enabled. ATtiny88 Automotive OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...
Page 108
... COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond- ing to the OC1A or OC1B pin must be set in order to enable the output driver. ATtiny88 Automotive 108 clk ...
Page 109
... Compare Match when downcounting special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 102. ATtiny88 Automotive shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected. Toggle OC1A/OC1B on Compare Match. ...
Page 110
... Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select ATtiny88 Automotive 110 Table 12-5. ...
Page 111
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – R/W R ATtiny88 Automotive – – – – Figure 0 – TCCR1C R 0 111 ...
Page 112
... TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A Bit Read/Write Initial Value ATtiny88 Automotive 112 TCNT1[15:8] TCNT1[7:0] ...
Page 113
... These bits are reserved and will always read zero. 9157B–AVR–01/ R/W R/W R See “Accessing 16-bit Registers” on page 88 R/W R/W R See “Accessing 16-bit Registers” on page 88 – – ICIE1 ATtiny88 Automotive OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R ICR1[15:8] ICR1[7:0] R/W R/W R/W R – ...
Page 114
... Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe- cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. ATtiny88 Automotive 114 43.) is executed when the TOV1 Flag, located in TIFR1, is set. ...
Page 115
... Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 9157B–AVR–01/10 ATtiny88 Automotive Table 12-5 on page 110 for the TOV1 115 ...
Page 116
... The edge detector generates one clk (CSn2 edge it detects. Figure 13-1. T1/T0 Pin Sampling Tn clk I/O ATtiny88 Automotive 116 and “16-bit Timer/Counter1 with PWM” on page 86 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization ...
Page 117
... Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1 clk I/O PSRSYNC T0 T1 Note: 9157B–AVR–01/10 < f /2) given a 50% duty cycle. Since the edge detector uses ExtClk clk_I/O Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ATtiny88 Automotive /2.5. clk_I/O (1) Clear T1 T1/T0) is shown in Figure clk T0 13-1. 117 ...
Page 118
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. ATtiny88 Automotive 118 7 6 ...
Page 119
... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 14.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATtiny88 and peripheral devices or between several AVR devices. Figure 14-1. SPI Block Diagram /2/4/8/16/32/64/128 Note: 9157B–AVR–01/10 (1) DIVIDER 1 ...
Page 120
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f ATtiny88 Automotive 120 “PRR – Power Reduction Register” on page 38 ...
Page 121
... SPCR,r17 ret ; Start transmission of data (r16) SPDR,r16 out ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret 1. See ”About Code Examples” on page 7. ATtiny88 Automotive Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 121 ...
Page 122
... The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: Note: ATtiny88 Automotive 122 (1) /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1< ...
Page 123
... The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. 9157B–AVR–01/10 (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; ATtiny88 Automotive 123 ...
Page 124
... Figure 14-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) ATtiny88 Automotive 124 Figure 14-4. MSB Bit 6 Bit 5 LSB Bit 1 Bit 2 MSB Bit 6 LSB Bit 1 ...
Page 125
... R/W R/W R Figure 14-3 and Figure 14-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling ATtiny88 Automotive Table 14-3 on page 125 below. Leading Edge Trailing eDge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising ...
Page 126
... WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved and will always read zero. ATtiny88 Automotive 126 Figure 14-3 CPHA Functionality ...
Page 127
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATtiny88 is also used for program memory and EEPROM downloading or uploading. See 14.5.3 SPDR – SPI Data Register ...
Page 128
... TWI Terminology The following definitions are frequently encountered in this section. Table 15-1. Term Master Slave Transmitter Receiver ATtiny88 Automotive 128 2 C Protocol Device 1 Device 2 Device 3 TWI Terminology Description The device that initiates and terminates a transmission and generates the SCL clock. ...
Page 129
... Power Reduction Register” on page 38 Figure 15-1, both bus lines are connected to the positive supply voltage through “2-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATtiny88 Automotive must be written to zero to 213. Two Data Stable 129 ...
Page 130
... A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. ATtiny88 Automotive 130 START ...
Page 131
... SLA+R/W and the STOP condition, depending on the software protocol imple- mented by the application software. 9157B–AVR–01/10 Data MSB 1 2 shows a typical data transmission. Note that several data bytes can be transmitted ATtiny88 Automotive Data LSB ACK Data Byte STOP, REPEATED ...
Page 132
... This will facilitate the arbitration process. Figure 15-7. SCL Synchronization Between Multiple Masters SCL from Master A SCL from Master B SCL Bus Line ATtiny88 Automotive 132 Addr MSB Addr LSB R/W ACK ...
Page 133
... This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 9157B–AVR–01/10 START ATtiny88 Automotive Master A Loses Arbitration, SDA SDA A ...
Page 134
... Register (TWSR). Slave operation does not depend on bit rate or prescaler settings, but the clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. ATtiny88 Automotive 134 SCL ...
Page 135
... SCL prescaled system clock, see Figure 6-1 on page 26 = system clock, see Figure 6-1 on page 26 Table 15-7 on page 157 In TWI Master mode TWBR must be 10, or higher . ATtiny88 Automotive “TWHSR – TWI High Speed clk I/O 2 TWBR TWPS clk TWIHS 2 TWBR TWPS “ ...
Page 136
... In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers. ATtiny88 Automotive 136 9157B–AVR–01/10 ...
Page 137
... TWCR, making sure that TWINT is written to one SLA TWINT set. Status code indicates SLA+W sent, ACK received ATtiny88 Automotive 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...
Page 138
... After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. ATtiny88 Automotive 138 9157B–AVR–01/10 ...
Page 139
... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATtiny88 Automotive Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register ...
Page 140
... The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is trans- mitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. ATtiny88 Automotive 140 to Figure 15-18, circles are used to indicate that the TWINT Flag is set ...
Page 141
... Device 3 MASTER SLAVE TRANSMITTER RECEIVER TWINT TWEA TWSTA TWSTO Table 15-2). In order to enter MT mode, SLA+W must be TWINT TWEA TWSTA TWSTO Table 15-2. TWINT TWEA TWSTA TWSTO ATtiny88 Automotive V CC ........ R1 Device n TWWC TWEN – TWWC TWEN – TWWC TWEN – TWIE X TWIE ...
Page 142
... NOT ACK has been received 0x28 Data byte has been transmit- ted; ACK has been received 0x30 Data byte has been transmit- ted; NOT ACK has been received 0x38 Arbitration lost in SLA+W or data bytes ATtiny88 Automotive 142 TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA ...
Page 143
... MT S SLA W A $08 $ $38 A $68 $78 DATA From master to slave From slave to master Figure 15-13). In order to enter a Master mode, a START condition must be transmit- ATtiny88 Automotive DATA $30 Other master Other master continues continues $38 Other master continues To corresponding ...
Page 144
... The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR value A REPEATED START condition is generated by writing the following value to TWCR: TWCR value ATtiny88 Automotive 144 Device 1 Device 2 Device 3 MASTER SLAVE ...
Page 145
... Read data byte Read data byte Read data byte ATtiny88 Automotive TWE Next Action Taken by TWI Hardware A X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to Master Transmitter mode ...
Page 146
... Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure are zero or are masked to zero. Figure 15-15. Data transfer in Slave Receiver mode SDA SCL ATtiny88 Automotive 146 MR S SLA R A DATA $08 $40 ...
Page 147
... Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. 9157B–AVR–01/10 TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATtiny88 Automotive TWA2 TWA1 TWA0 TWGCE TWWC TWEN – Table TWIE X 15-4. 147 ...
Page 148
... Previously addressed with general call; data has been received; NOT ACK has been returned 0xA0 A STOP condition or repeated START condition has been received while still addressed as Slave ATtiny88 Automotive 148 Application Software Response To TWCR To/from TWDR STA STO TWIN T No TWDR action or ...
Page 149
... A $68 General Call A $70 A $78 DATA From master to slave From slave to master n 15-17). All the status codes mentioned in this section assume that the prescaler bits Device 1 Device 2 Device 3 SLAVE MASTER TRANSMITTER RECEIVER ATtiny88 Automotive DATA A DATA $80 $80 $ $88 DATA A DATA $90 $90 $A0 ...
Page 150
... Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. ATtiny88 Automotive 150 TWA6 TWA5 ...
Page 151
... No TWDR action TWDR action ATtiny88 Automotive TWE Next Action Taken by TWI Hardware A 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...
Page 152
... Status of the 2-wire Serial Bus Prescaler Bits and 2-wire Serial Interface are 0 Hardware 0xF8 No relevant state information available; TWINT = “0” 0x00 Bus error due to an illegal START or STOP condition ATtiny88 Automotive 152 S SLA R A $A8 A $B0 DATA From master to slave From slave to master ...
Page 153
... An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver. 9157B–AVR–01/10 Master Transmitter SLA+W A ADDRESS Transmitted from master to slave ATtiny88 Automotive Master Receiver A Rs SLA+R A DATA Rs = REPEATED START Transmitted from slave to master ...
Page 154
... READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. This is summarized in Figure 15-21. Possible Status Codes Caused by Arbitration START ATtiny88 Automotive 154 Device 1 Device 3 Device 2 MASTER ...
Page 155
... TWBR7 TWBR6 TWBR5 TWBR4 R/W R/W R/W R for calculating bit rates TWINT TWEA TWSTA TWSTO R/W R/W R/W R ATtiny88 Automotive TWBR3 TWBR2 TWBR1 TWBR0 R/W R/W R/W R “Bit Rate Generator TWWC TWEN – TWIE R R TWBR ...
Page 156
... The application designer should mask the pres- caler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. ATtiny88 Automotive 156 ...
Page 157
... Serial Bus. 9157B–AVR–01/10 TWI Bit Rate Prescaler TWPS0 “Bit Rate Generator Unit” on page TWD7 TWD6 TWD5 TWD4 R/W R/W R/W R ATtiny88 Automotive Prescaler Value 134. The value of TWPS1.. TWD3 TWD2 TWD1 TWD0 R/W R/W R/W R TWDR 157 ...
Page 158
... TWAR. detail. Figure 15-22. TWI Address Match Logic, Block Diagram • Bit 0 – Res: Reserved Bit These bits are reserved and will always read zero. ATtiny88 Automotive 158 TWA6 ...
Page 159
... Figure 6-1 on page . This means the user must make sure the I/O clock I/O is scaled down by a factor of 2. For example, if the internal 8 MHz oscillator has I/O 26. ATtiny88 Automotive – – – TWHS R 26 exactly two times ...
Page 160
... ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in 16-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. ATtiny88 Automotive 160 Figure 16-1. ...
Page 161
... ADC6 0 111 ADC7 – ACME – – “Analog Comparator Multiplexed Input” on page ACD ACBG ACO ACI R/W R N/A 0 ATtiny88 Automotive – ADTS2 ADTS1 ADTS0 R R/W R/W R 160 ACIE ACIC ACIS1 ACIS0 R/W R/W R/W R ADCSRB ACSR 161 ...
Page 162
... When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATtiny88 Automotive 162 See “Internal Voltage Reference” on page 43. Table 16-2. ACIS1/ACIS0 Settings ...
Page 163
... AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. 9157B–AVR–01/ – – – – ATtiny88 Automotive – – AIN1D AIN0D R R R/W R DIDR1 163 ...
Page 164
... Sleep Mode Noise Canceler 17.2 Overview ATtiny88 features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The ADC is wired to a nine-channel analog multiplexer, which allows the ADC to measure the volt- age at six (or eight, in 32-lead packages) single-ended input pins and from one internal, single-ended voltage channel coming from the internal temperature sensor. Single-ended volt- age inputs are referred to 0V (GND) ...
Page 165
... SELECT (ADMUX) MUX DECODER REFERENCE BANDGAP SENSOR INPUT MUX for more details. supply pin and the internal 1.1V voltage reference. CC ATtiny88 Automotive ADC CONVERSION COMPLETE IRQ 15 ADC DATA REGISTER ADC CTRL. & STATUS REGISTER (ADCSRA) (ADCH/ADCL) PRESCALER CONVERSION LOGIC SAMPLE & HOLD ...
Page 166
... Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ATtiny88 Automotive 166 “PRR – Power Reduction Register” on page 38). A single conver- ...
Page 167
... Figure 17-3. ADC Prescaler 9157B–AVR–01/10 ADTS[2:0] ADIF SOURCE EDGE DETECTOR SOURCE n ADSC ADEN Reset START CK ADPS0 ADPS1 ADPS2 ATtiny88 Automotive PRESCALER START ADATE CONVERSION LOGIC 7-BIT ADC PRESCALER ADC CLOCK SOURCE CLK ADC 167 ...
Page 168
... ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. Figure 17-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATtiny88 Automotive 168 Figure 17-4 below. First Conversion ...
Page 169
... Sample & Prescaler Hold Reset MUX and REFS Update Figure One Conversion 12 13 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete ATtiny88 Automotive One Conversion Conversion Complete 17-7. Next Conversion Sign and MSB of Result LSB of Result Sample & Hold ...
Page 170
... In Single Conversion mode, always select the channel before starting the conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. ATtiny88 Automotive 170 Table 17-1 ...
Page 171
... S/H capacitor. 9157B–AVR–01/10 ) indicates the conversion range for the ADC. Single ended REF will result in codes close to 0x3FF. V REF ) through an internal amplifier. BG ATtiny88 Automotive can be selected as either REF Figure 17-8 An analog 171 ...
Page 172
... Keep analog tracks well away from high-speed switching digital tracks. • If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress. • The analog supply voltage pin ( ATtiny88 Automotive 172 /2) should not be present. The user is advised to remove high fre- ADC I ...
Page 173
... LSB). Ideal value: 0 LSB. 9157B–AVR–01/10 Section 17.7 on page 171. This is especially the case when system clock frequency Section 17.12 on page 176. A good system design with properly placed, external ATtiny88 Automotive PC1 (ADC1) PC0 (ADC0) VCC PA1 (ADC7) GND ...
Page 174
... Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 17-11. Gain Error Output Code ATtiny88 Automotive 174 Offset Error Ideal ADC ...
Page 175
... Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 17-13. Differential Non-linearity (DNL) 9157B–AVR–01/10 Output Code 0x3FF 1 LSB 0x000 0 ATtiny88 Automotive Ideal ADC Actual ADC V Input Voltage REF V Input Voltage REF ...
Page 176
... ADCH and ADCL are the ADC data registers the fixed slope coefficient and T temperature sensor offset. Typically very close to 1.0 and in single-point calibration the coefficient may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measurements at two temperatures. ATtiny88 Automotive 176 ADC is the voltage on the selected input pin and V ...
Page 177
... Input Channel Selections MUX3..0 Single Ended Input 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 ATtiny88 Automotive MUX3 MUX2 MUX1 MUX0 R/W R/W R/W R Table 17-3. If this bit is changed “ADCL and ADCH – The ADC Data Register” on ...
Page 178
... ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter- natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. ATtiny88 Automotive 178 Input Channel Selections (Continued) MUX3..0 ...
Page 179
... ADC Prescaler Selections ADPS1 ADPS0 – – – ADC7 ADC6 ADC5 ADC9 ADC8 ADC7 ADC1 ADC0 – ATtiny88 Automotive Division Factor 128 – – – ADC9 ADC4 ADC3 ADC2 ADC1 ADC6 ADC5 ADC4 ADC3 – – – – “ADC Conversion Result” on ...
Page 180
... If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 17-6. ADTS2 ATtiny88 Automotive 180 – ...
Page 181
... ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 9157B–AVR–01/ ADC7D ADC6D ADC5D ADC4D R/W R/W R/W R ATtiny88 Automotive ADC3D ADC2D ADC1D ADC0D R/W R/W R/W R DIDR0 181 ...
Page 182
... Figure 18-1. The debugWIRE Setup Figure 18-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. ATtiny88 Automotive 182 dW dW(RESET) GND shows the schematic of a target MCU, with debugWIRE enabled, and the emulator 1 ...
Page 183
... This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. 9157B–AVR–01/10 will not work. CC ® will insert a BREAK instruction in the Program memory. The instruc DWDR[7:0] R/W R/W R/W R ATtiny88 Automotive R/W R/W R/W R DWDR 183 ...
Page 184
... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. ATtiny88 Automotive 184 9157B–AVR–01/10 ...
Page 185
... Figure 19-1. Note that the Page Erase and Page Write operations are BIT 15 ZPCMSB PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE 1. The different variables used in Figure 19-1 ATtiny88 Automotive Z12 Z11 Z10 Table 20-7 on page ...
Page 186
... Fuse Extended Byte (FEB) will be loaded in the destination register as shown below. See byte. Bit Rd Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. ATtiny88 Automotive 186 – – ...
Page 187
... Lock bits by SPM) 19.1.5 Simple Assembly Code Example for a Boot Loader Note that the RWWSB bit will always be read as zero in ATtiny88. Nevertheless, to ensure com- patibility with devices supporting Read-While-Write it is recommended to check this bit as shown in the code example. ;-the routine writes one page of data from RAM to Flash ...
Page 188
... RWW section ldi rcallDo_spm rjmp Return Do_spm: ; check for previous SPM complete Wait_spm: in ATtiny88 Automotive 188 spmcrval, (1<<PGERS) | (1<<SELFPRGEN) spmcrval, (1<<CTPB) | (1<<SELFPRGEN) looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 r0, Y+ r1, Y+ spmcrval, (1< ...
Page 189
... Register, will read either the Lock bits or the Fuse bits (depending the Z-pointer) into the destination register. See details. 9157B–AVR–01/10 temp2, SREG SPMCSR, spmcrval SREG, temp2 RWWSB – CTPB R “Reading the Fuse and Lock Bits from Software” on page 186 ATtiny88 Automotive RFLB PGWRT PGERS SELFPRGEN R/W R/W R/W R SPMCSR for 189 ...
Page 190
... SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SELFPRGEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. ATtiny88 Automotive 190 9157B–AVR–01/10 ...
Page 191
... Program And Data Memory Lock Bits The ATtiny88 provides two Lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional features listed in erased to “1” with the Chip Erase command. The ATtiny88 has no separate Boot Loader section. ...
Page 192
... Fuse Bits The ATtiny88 has three Fuse bytes. all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi- cal zero, “0”, if they are programmed. Table 20-3. Fuse Extended Byte – ...
Page 193
... Calibration Byte The ATtiny88 has a byte calibration value for the internal oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated oscillator. ...
Page 194
... Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny88. Pulses are assumed least 250 ns unless otherwise noted. 20.6.1 Signal Names ...
Page 195
... Load Flash or EEPROM Address (High or low address byte determined by BS1). 1 Load Data (High or Low data byte for Flash determined by BS1). 0 Load Command 1 No Action, Idle ATtiny88 Automotive I/O Function 0: Device is busy programming, 1: Device is O ready for new command I Output Enable (Active low) ...
Page 196
... Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Wait until V commands. 6. Exit Programming mode by power the device down or by bringing RESET pin to 0V. ATtiny88 Automotive 196 Table 20-12. Command Executed ...
Page 197
... Give CLKI a positive pulse. This loads the address low byte. 9157B–AVR–01/10 The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Table 20-7 on page ATtiny88 Automotive (Note:) memories plus Lock bits. The Lock bits 194. When programming the Flash, ...
Page 198
... Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. ATtiny88 Automotive 198 Figure 20-3 Figure 20-2 on page 199. Note that if less than Figure 20-3 for signal waveforms) ...
Page 199
... PAGE 1. PCPAGE and PCWORD are listed 0x10 ADDR. LOW DATA LOW DATA HIGH XX 1. “XX” is don’t care. The letters refer to the programming description above. ATtiny88 Automotive (1) PAGEMSB PCWORD WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD Table 20-7 on page 194. ( ...
Page 200
... Wait until to RDY/BSY goes high before programming the next page (See for signal waveforms). Figure 20-4. Programming the EEPROM Waveforms DATA XA1 XA0 BS1 CLKI WR RDY/BSY RESET +12V OE PAGEL BS2 ATtiny88 Automotive 200 Table 20-8 on page “Programming the Flash” on page 197 0x11 ADDR. HIGH ADDR. LOW DATA XX 194 ...