ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 199
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATmega88
Manufacturer Part Number
ATmega88
Description
Manufacturer
Atmel Corporation
Specifications of ATmega88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega88-15AT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega88-15AT1
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
ATmega88-15AT1
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega88-15ATI
Manufacturer:
ATMEL
Quantity:
5 510
Company:
Part Number:
ATmega88-15ATI
Manufacturer:
LT
Quantity:
5 510
Company:
Part Number:
ATmega88-15AZ
Manufacturer:
ATMEL
Quantity:
2 000
Company:
Part Number:
ATmega88-15AZ
Manufacturer:
ATMEL
Quantity:
120
Part Number:
ATmega88-15AZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega88-20AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
21. USART in SPI mode
21.1
21.2
21.3
2545T–AVR–05/11
Features
Overview
Clock generation
•
•
•
•
•
•
•
•
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation. Setting both UMSELn1:0 bits to one enables
the USART in Master SPI Mode (MSPIM) logic. In this mode of operation the SPI master control
logic takes direct control over the USART resources. These resources include the transmitter
and receiver shift register and buffers, and the baud rate generator. The parity generator and
checker, the data and clock recovery logic, and the RX and TX control logic is disabled. The
USART RX and TX control logic is replaced by a common SPI transfer control logic. However,
the pin control logic and interrupt generation logic is identical in both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (that is, master operation) is
supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to
one (that is, as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn
should be set up before the USART in MSPIM is enabled (that is, TXENn and RXENn bit set to
one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see
Full duplex, three-wire synchronous data transfer
Master operation
Supports all four SPI modes of operation (mode 0, 1, 2, and 3)
LSB first or MSB first data transfer (configurable data order)
Queued operation (double buffered)
High resolution baud rate generator
High speed operation (fXCKmax = fCK/2)
Flexible interrupt generation
Table 21-1 on page
200:
ATmega48/88/168
199