ATmega64RZAPV Atmel Corporation, ATmega64RZAPV Datasheet - Page 89
ATmega64RZAPV
Manufacturer Part Number
ATmega64RZAPV
Description
Manufacturer
Atmel Corporation
Specifications of ATmega64RZAPV
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
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8011O–AVR–07/10
• INT0/RXD1/PCINT26 – Port D, Bit 2
INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the
MCU.
RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is
enabled this pin is configured as an input regardless of the value of DDD2. When the USART
forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.
PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as an external interrupt
source.
• TXD0/PCINT25 – Port D, Bit 1
TXD0, Transmit Data (Data output pin for the USART0). When the USART0 Transmitter is
enabled, this pin is configured as an output regardless of the value of DDD1.
PCINT25, Pin Change Interrupt Source 25: The PD1 pin can serve as an external interrupt
source.
• RXD0/PCINT24 – Port D, Bit 0
RXD0, Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled
this pin is configured as an input regardless of the value of DDD0. When the USART forces this
pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt
source.
Table 11-13 on page 89
the overriding signals shown in
Table 11-13. Overriding Signals for Alternate Functions PD7:PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PD7/OC2A/
PCINT31
0
0
0
0
OC2A ENABLE
OCA2A
PCINT31 • PCIE3
1
PCINT31 INPUT
–
and
Table 11-14 on page 90
Figure 11-5 on page
PD6/ICP1/
OC2B/
PCINT30
0
0
0
0
OC2B ENABLE
OC2B
PCINT30 • PCIE3
1
ICP1 INPUT
PCINT30 INPUT
–
ATmega164P/324P/644P
78.
relates the alternate functions of Port D to
PD5/OC1A/
PCINT29
0
0
0
0
OC1A ENABLE
OC1A
PCINT29 • PCIE3
1
PCINT29 INPUT
–
PD4/OC1B/XCK1/
PCINT28
0
0
0
0
OC1B ENABLE
OC1B
PCINT28 • PCIE3
1
PCINT28 INPUT
–
89
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