ATmega64RZAPV Atmel Corporation, ATmega64RZAPV Datasheet - Page 334

• Manufacturer Part Number: ATmega64RZAPV
• Manufacturer: Atmel Corporation

Specifications of ATmega64RZAPV

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

Table 25-10. 2-wire Serial Bus Requirements (Continued)
Notes:
8011O–AVR–07/10
Symbol
t
t
t
t
t
t
t
t
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
1. In ATmega164P/324P/644P, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Other devices connected to the Two-wire
6. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater
7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time require-
Serial Bus need only obey the general fSCL requirement.
than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
ment will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega32 devices connected to the bus may
communicate at full speed (400 kHz) with other ATmega32 devices, as well as any other device with a proper tLOW accep-
tance margin.
Parameter
Hold Time (repeated) START Condition
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
Figure 25-6. 2-wire Serial Bus Timing
SCL
SDA
t
SU;STA
t
HD;STA
t
t
of
LOW
f
f
SCL
SCL
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Condition
≤ 100 kHz
> 100 kHz
t
HIGH
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
t
HD;DAT
(6)
(7)
t
LOW
ATmega164P/324P/644P
t
SU;DAT
250
100
Min
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
0
0
t
SU;STO
t
r
3.45
Max
0.9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
t
BUF
Units
µs
ns
µs
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