ATmega64RZAPV Atmel Corporation, ATmega64RZAPV Datasheet - Page 158
ATmega64RZAPV
Manufacturer Part Number
ATmega64RZAPV
Description
Manufacturer
Atmel Corporation
Specifications of ATmega64RZAPV
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
0.25
Antenna Diversity
No
External Pa Control
No
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
16.0
Transmit Current Consumption (ma)
17.0
Link Budget (dbm)
104
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14.11.7
8011O–AVR–07/10
TIMSK2 – Timer/Counter2 Interrupt Mask Register
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.
When TCCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new
value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A
and TCCR2B the value in the temporary storage register is read.
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the
Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Inter-
rupt Flag Register – TIFR2.
Bit
(0x70)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
ATmega164P/324P/644P
R
3
–
0
OCIE2B
R/W
2
0
OCIE2A
R/W
1
0
TOIE2
R/W
0
0
TIMSK2
158
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