ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 36
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ATmega325
Manufacturer Part Number
ATmega325
Description
Manufacturer
Atmel Corporation
Specifications of ATmega325
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Company
Part Number
Manufacturer
Quantity
Price
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20 000
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Part Number:
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Part Number:
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Manufacturer:
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Part Number:
ATmega3250-16AU
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Part Number:
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Quantity:
20 000
10.3
10.4
10.5
2570N–AVR–05/11
ADC Noise Reduction Mode
Power-down Mode
Power-save Mode
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI
start condition detection, Timer/Counter2, and the Watchdog to continue operating (if enabled).
This sleep mode basically halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a USI start condition interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready inter-
rupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from
ADC Noise Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the
USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-
nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level
interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically
halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 controller is enabled, it will keep running during sleep. The device can wake
up from either Timer Overflow or Output Compare event from Timer/Counter2 if the correspond-
ing Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit
in SREG is set.
If the Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save
mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save
mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is
stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is
stopped during sleep. Note that even if the synchronous clock is running in Power-save, this
clock is only available for Timer/Counter2.
I/O
, clk
“Clock Sources” on page
CPU
, and clk
ATmega325/3250/645/6450
FLASH
, while allowing the other clocks to run.
“External Interrupts” on page 55
27.
36