ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 285
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ATmega325
Manufacturer Part Number
ATmega325
Description
Manufacturer
Atmel Corporation
Specifications of ATmega325
Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega325-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega325-16AU
Manufacturer:
ATMEL
Quantity:
231
Part Number:
ATmega325-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega3250-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega3250-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega3250P-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
27.8.1
27.8.2
2570N–AVR–05/11
Programming Specific JTAG Instructions
AVR_RESET (0xC)
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
Figure 27-13. State Machine Sequence for Changing the Instruction Word
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking
the device out from the Reset mode. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the reset will be active as long as there
is a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
•
Shift-DR: The Reset Register is shifted by the TCK input.
1
0
Test-Logic-Reset
Run-Test/Idle
0
Figure
1
27-13.
1
0
Select-DR Scan
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
ATmega325/3250/645/6450
1
0
0
1
0
1
1
0
1
1
0
0
1
0
Select-IR Scan
Capture-IR
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
1
0
0
1
0
1
1
0
1
1
0
0
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