AT90USB1286 Atmel Corporation, AT90USB1286 Datasheet - Page 355
AT90USB1286
Manufacturer Part Number
AT90USB1286
Description
Manufacturer
Atmel Corporation
Specifications of AT90USB1286
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
48
Ext Interrupts
16
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
10
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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28.5.4
7593K–AVR–11/09
Store Program Memory Control and Status Register – SPMCSR
Figure 28-3. Boot Process Description
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see
the Signature Row from Software” on page 360
Bit
Read/Write
Initial Value
7
SPMIE
R/W
0
Reset Vector = Application Reset
6
RWWSB
R
0
BOOTRST ?
HWBE
5
SIGRD
R/W
0
?
4
RWWSRE
R/W
0
3
BLBSET
R/W
0
for details. An SPM instruction within four cycles
ALE/HWB
RESET
2
PGWRT
R/W
0
Ext. Hardware
Conditions ?
Reset Vector =Boot Lhoader Reset
1
PGERS
R/W
0
AT90USB64/128
t
SHRH
0
SPMEN
R/W
0
SPMCSR
t
HHRH
“Reading
355
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