AT90USB1286 Atmel Corporation, AT90USB1286 Datasheet - Page 268
AT90USB1286
Manufacturer Part Number
AT90USB1286
Description
Manufacturer
Atmel Corporation
Specifications of AT90USB1286
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
48
Ext Interrupts
16
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
10
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90USB1286
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT90USB1286-AU
Manufacturer:
SOUTH
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650
Part Number:
AT90USB1286-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT90USB1286-AUR
Manufacturer:
Atmel
Quantity:
747
Company:
Part Number:
AT90USB1286-MU
Manufacturer:
ATMEL
Quantity:
716
Part Number:
AT90USB1286-MU
Manufacturer:
AT
Quantity:
20 000
Company:
Part Number:
AT90USB1286-MUR
Manufacturer:
Atmel
Quantity:
4 932
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22.4
22.5
22.6
268
USB reset
Endpoint selection
Endpoint activation
AT90USB64/128
The data toggle field remains unchanged.
The other registers remain unchanged.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as
an answer to the CLEAR_FEATURE USB command.
When an USB reset is detected on the USB line, the next operations are performed by the
controller:
Prior to any operation performed by the CPU, the endpoint must first be selected. This is done
by setting the EPNUM2:0 bits (UENUM register) with the endpoint number which will be man-
aged by the CPU.
The CPU can then access to the various endpoint registers and data.
The endpoint is maintained under reset as long as the EPEN bit is not set.
The following flow must be respected in order to activate an endpoint:
• the UEINTX, UESTA0X and UESTA1X are restored to their reset value.
• all the endpoints are disabled
• the default control endpoint remains configured (see Section 22.3, page 267 for more
details).
7593K–AVR–11/09
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