AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 96

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

17.4
Figure 17-3. SPI Transfer Format with CPHA = 0
Note:
Figure 17-4. SPI Transfer Format with CPHA = 1
Note:
96
Serial Clock Timing
*Not defined but normally MSB of character just received.
*Not defined but normally LSB of previously transmitted character.
(FOR REFERENCE)
AT89LP428/828
(FROM MASTER)
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
(FROM SLAVE)
SCK CYCLE #
MOSI
MISO
The TSCK, CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two
SPR bits provide four possible bit clock rates when the SPI is in master mode. The TSCK bit
also allows a timer-generated bit rate. In slave mode, the SPI will operate at the rate of the
incoming SCK as long as it does not exceed the maximum bit rate. There are also four possible
combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL deter-
mine which format is used for transmission. The SPI data transfer formats are shown in
17-3 and
SPR should not be modified while the interface is enabled, and the master device should be
enabled before selecting the slave device(s).
*
17-4. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL, and
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
8
LSB
LSB
3654A–MICRO–8/09
Figures