AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 28

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AT89LP828

Manufacturer Part Number
AT89LP828
Description
Manufacturer
Atmel Corporation
Datasheet

Specifications of AT89LP828

Flash (kbytes)
8 Kbytes
Max. Operating Frequency
25 MHz
Cpu
8051-1C
Max I/o Pins
30
Spi
1
Uart
1
Sram (kbytes)
0.75
Eeprom (bytes)
1024
Self Program Memory
IAP
Operating Voltage (vcc)
2.4 to 5.5
Timers
3
Isp
SPI/OCD
Watchdog
Yes

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8.2.2
28
AT89LP428/828
Reset Recovery from Power-down
Figure 8-2.
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in
propagate to the CPU until after the timer has timed out. The time-out period is controlled by the
Start-up Timer Fuses. (See
clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will
remain in reset until RST is brought high.
Figure 8-3.
.
Internal
Internal
XTAL1
Reset
Interrupt Recovery from Power-down (PWDEX = 1)
Internal
Reset Recovery from Power-down
Clock
PWD
XTAL1
RST
Clock
PWD
INT1
Table 7-1 on page
Figure
25). If RST returns high before the time-out, a two
8-3. The internal clock will not be allowed to
t SUT
3654A–MICRO–8/09

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