AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 106

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

19.1
Table 19-2.
Table 19-3.
106
WDTCON Address = A7H
Not Bit Addressable
Bit
Symbol
PS2
PS1
PS0
WDIDLE
SWRST
WDTOVF
WDTEN
WDTRST Address = A6H
Not Bit Addressable
Bit
The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by
reading the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must
be written to WDTRST before the time-out interval expires. A software reset is generated by writing the sequence
5AH/A5H to WDTRST.
Software Reset
AT89LP428/828
PS2
–
7
7
Function
Prescaler Bits for the Watchdog Timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
Disable/enable the Watchdog Timer in IDLE Mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When
WDIDLE = 1, WDT freezes while the device is in IDLE mode.
Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set
when an incorrect sequence is written to WDTRST. Must be cleared by software.
Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect
sequence is written to WDTRST. Must be cleared by software.
Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The
WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST
WDTCON – Watchdog Control Register
WDTRST – Watchdog Reset Register
PS1
6
–
6
A Software Reset of the AT89LP428/828 is accomplished by writing the software reset
sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate
the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at
any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or
5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF
flags will be set. In this manner an intentional software reset may be distinguished from a soft-
ware error-generated reset. The program sequence to generate a software reset is as follows:
PS0
–
5
5
MOV WDTRST, #05Ah
MOV WDTRST, #0A5h
WDIDLE
4
–
4
–
–
3
3
SWRST
2
–
2
Reset Value = 0000 X000B
WDTOVF
1
–
1
(Write-Only)
WDTEN
3654A–MICRO–8/09
–
0
0