AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 62

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AT89LP4052

Manufacturer Part Number
AT89LP4052
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89LP4052

Flash (kbytes)
4 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
15
Spi
1
Uart
1
Sram (kbytes)
0.25
Operating Voltage (vcc)
2.4 to 5.5
Timers
2
Isp
SPI
Watchdog
Yes

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23.4.3
23.4.4
62
AT89LP2052/LP4052
Program Enable
Chip Erase
Function:
Usage:
Figure 23-7. Program Enable Sequence
Function:
Usage:
Figure 23-8. Chip Erase Sequence
Note:
• Enables the programming interface to receive commands.
• Program Enable must be the first command issued in any programming session. In parallel
1. Bring CS (P3.2) low.
2. Drive P1 to AAh and pulse XTAL1 high.
3. Drive P1 to ACh and pulse XTAL1 high.
4. Drive P1 to 53h and pulse XTAL1 high.
5. Bring CS high.
• Erases (programs FFh to) the entire 2/4-Kbyte memory array.
• Erases User Signature Row if User Row Programming Fuse bit is enabled.
• Lockbit1 and Lockbit2 are programmed to “unlock” state.
1. Bring CS (P3.2) low.
2. Drive P1 to AAh and pulse XTAL1 high.
3. Drive P1 to 8Ah and pulse XTAL1 high.
4. Bring CS high.
5. Wait 4 ms, monitor P3.1, or poll data/status.
programming a session is active while RST remains at V
is active while RST remains at V
RDY/BSY
XTAL1
XTAL1
The waveforms on this page are not to scale.
CS
P1
CS
P1
AAh
AAh
CC
ACh
.
8Ah
53h
PP
. In serial programming a session
3547J–MICRO–10/09

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