AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 18

• Manufacturer Part Number: AT89LP4052
• Manufacturer: Atmel Corporation

Specifications of AT89LP4052

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 15
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI
• Watchdog: Yes

If a request is active and conditions are met for it to be acknowledged, a hardware subroutine
call to the requested service routine will be the next instruction executed. The call itself takes
four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an
interrupt request and the beginning of execution of the first instruction of the service routine.
A longer response time results if the request is blocked by one of the previously listed condi-
tions. If an interrupt of equal or higher priority level is already in progress, the additional wait time
depends on the nature of the other interrupt's service routine. If the instruction in progress is not
in its final clock cycle, the additional wait time cannot be more than 3 cycles, since the longest
are only 4 cycles long. If the instruction in progress is RETI or an access to IE or IP, the addi-
tional wait time cannot be more than 7 cycles (a maximum of three more cycles to complete the
instruction in progress, plus a maximum of 4 cycles to complete the next instruction). Thus, in a
single-interrupt system, the response time is always more than 5 clock cycles and less than
13 clock cycles. See
Figures 14-1 and
14-2.
Figure 14-1. Minimum Interrupt Response Time
Clock Cycles
1
5
INT0
IE0
Ack.
Instruction
Cur. Instr.
LCALL
1st ISR Instr.
Figure 14-2. Maximum Interrupt Response Time
Clock Cycles
1
13
INT0
IE0
Ack.
Instruction
RETI
4 Cyc. Instr.
LCALL
1st ISR In
AT89LP2052/LP4052
18
3547J–MICRO–10/09