AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 52

• Manufacturer Part Number: AT89C51CC01
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC01

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 1.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Automatic Address
Recognition
52
A/T89C51CC01
Figure 29. UART Timing in Mode 1
Figure 30. UART Timing in Modes 2 and 3
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces-
sor communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address will the
receiver set the RI bit in the SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If necessary, you can enable the automatic address recognition feature in mode 1. In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
SMOD0=0
SMOD0=1
SMOD0=1
SMOD0=X
SMOD0=1
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
RXD
RXD
FE
RI
RI
FE
RI
Start
Start
bit
bit
D0
D0
D1
D1
D2
D2
D3
D3
Data byte
Data byte
D4
D4
D5
D5
D6
D6
D7
D7
Ninth
Stop
D8
bit
bit
4129N–CAN–03/08
Stop
bit