AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 19

• Manufacturer Part Number: AT89C51CC01
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC01

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 1.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Warm Reset
Watchdog Reset
Reset Recommendation
to Prevent Flash
Corruption
Idle Mode
Entering Idle Mode
Exiting Idle Mode
4129N–CAN–03/08
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
As detailed in Section “PCA Watchdog Timer”, page 123, the WDT generates a 96-clock
period pulse on the RST pin. In order to properly propagate this pulse to the rest of the
application in case of external capacitor or power-supply supervisor circuit, a 1KΩ resis-
tor must be added as shown Figure 8.
Figure 8. Reset Circuitry for WDT reset out usage
An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a flash access
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 14.
To enter Idle mode, you must set the IDL bit in PCON register (see Table 15). The
T89C51CC01 enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
–
If IDL bit and PD bit are set simultaneously, the T89C51CC01 enters Power-down mode.
Then it does not go in Idle mode when exiting Power-down mode.
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
VDD
VDD
VSS
+
RST
1K
RST
VSS
To CPU core
and peripherals
To other
on-board
circuitry
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