AT89C51CC01 Atmel Corporation, AT89C51CC01 Datasheet - Page 5
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AT89C51CC01
Manufacturer Part Number
AT89C51CC01
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C51CC01.pdf
(167 pages)
2.AT89C51CC01.pdf
(12 pages)
3.AT89C51CC01.pdf
(32 pages)
4.AT89C51CC01.pdf
(29 pages)
Specifications of AT89C51CC01
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
34
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
1.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes
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Read-Modify-Write
Instructions
4129N–CAN–03/08
Figure 2. Port 0 Structure
Notes:
Figure 3. Port 2 Structure
Notes:
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal
switches the output-driver input from the latch output to the internal address/data line.
Some instructions read the latch data rather than the pin data. The latch based instruc-
tions read the data, modify the data and then rewrite the latch. These are called "Read-
Modify-Write" instructions. Below is a complete list of these special instructions (see
Table ). When the destination operand is a Port or a Port bit, these instructions read the
latch rather than the pin:
READ
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
READ
PIN
READ
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
READ
PIN
1. Port 0 is precluded from use as general-purpose I/O Ports when used as
2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only.
1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus
2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for
address/data bus drivers.
Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.
drivers.
memory bus cycle.
D
LATCH
P0.X
D
LATCH
P2.X
ADDRESS LOW/
DATA
Q
ADDRESS HIGH/ CONTROL
Q
CONTROL
1
0
1
0
VDD
VDD
(2)
INTERNAL
PULL-UP (2)
P0.x (1)
P2.x (1)
5