AT83EB5114 Atmel Corporation, AT83EB5114 Datasheet - Page 54

• Manufacturer Part Number: AT83EB5114
• Manufacturer: Atmel Corporation

Specifications of AT83EB5114

• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 11
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 50
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Mask Rom (kbytes): 4
• Watchdog: Yes

WatchDog Timer
Figure 24. WatchDog Timer
54
AT89/83EB5114
F
CPU_PERIPH
RESET
-
-
AT8xEB5114 contains a powerful programmable hardware WatchDog Timer (WDT) that
automatically resets the chip if its software fails to reset the WDT before the selected
time interval has elapsed. It permits large Time-Out ranking from 16 ms to 2s @Fosc =
12 MHz.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a WatchDog
Timer reset register (WDTRST) and a WatchDog Timer programmation (WDTPRG) reg-
ister. When exiting reset, the WDT is -by default- disabled. To enable the WDT, the user
has to write the sequence 1EH and E1H into WDRST register. When the WatchDog
Timer is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or
WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xT
best use of the WDT, it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
The WDT is controlled by two registers (WDTRST and WDTPRG)
-
WDTRST
WDTPRG
-
14-bit COUNTER
Enable
-
2
1
0
WR
Control
Decoder
7-bit COUNTER
OSC
Outputs
, where T
OSC
=1/F
OSC
RESET
. To make the
4311C–8051–02/08