AT83EB5114 Atmel Corporation, AT83EB5114 Datasheet - Page 20

• Manufacturer Part Number: AT83EB5114
• Manufacturer: Atmel Corporation

Specifications of AT83EB5114

• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 11
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 50
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Mask Rom (kbytes): 4
• Watchdog: Yes

Exit from Idle Mode
Quiet Mode
Power-down Mode
Entering Power-down Mode
Exit from Power-down Mode
Figure 6. Power-down Exit Waveform
20
AT89/83EB5114
INTERRUPT
OSC
Active phase
their data during Idle. The port pins hold the logical states they had at the time Idle was
activated. ALE and PSEN are held at logic high levels. The different operating modes
are summarized on Table 10 on page 21.
There are two ways to terminate idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by hardware, terminating Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle. Exit from idle mode will leave the oscillators
control bits on OSCON and CKS registers unchanged.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during an Idle mode. For example, an instruction that activates
Idle mode can also set one or both flag bits. When Idle is terminated by an interrupt, the
interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
In both cases, PCON.0 is cleared by hardware.
The quiet mode is a pseudo idle mode in which the CPU and all the peripherals except
the AD converter are down. For more details, See “Analog-to-Digital Converter (ADC)”
on page 57.
To save maximum power, a power-down mode can be invoked by software (refer to
Table 11 on page 22). In power-down mode, the oscillator is stopped and the instruction
that invoked power-down mode is the last instruction executed. The internal RAM and
SFRs retain their value until the power-down mode is terminated. V
save further power.
An instruction that sets PCON.1 causes that to be the last instruction executed before
going into the power-down mode.
The ports status under power-down is the previous status before entering this power
mode.
Either a hardware reset or an external interrupt (low level) on INT0 or INT1 (if enabled)
can cause an exit from power-down. To properly terminate power-down, the reset or
external interrupt should not be executed before V
level and must be held active long enough for the oscillator to restart and stabilize.
Exit from power-down by external interrupt does not affect the SFRs and the internal
RAM content.
By a hardware Reset, the CPU will restart in the mode defined by the RST_OSC1 and
RST_OSC0 bits in HSB.
Power-down phase
Oscillator restart phase
CC
is restored to its normal operating
Active phase
CC
can be lowered to
4311C–8051–02/08