AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 78
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AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2256C-A2UR
Manufacturer:
Cirrus
Quantity:
48
Part Number:
AT32UC3C2256C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C2256C-Z
Manufacturer:
ATMEL
Quantity:
261
Company:
Part Number:
AT32UC3C2256C-Z2UR
Manufacturer:
ATMEL
Quantity:
93
32002F–03/2010
The stcond instruction takes 2 cycles if the store is not performed, 3 cycles if the store is
performed.
All issue latencies are given for accesses to IRAM or LOCAL. These timings must be modified
as follows for accesses to BOOT or HSB sections:
Table 8-7.
Mnemonics
ld.ub
ld.ub{cond4}
ld.sb
ld.sb{cond4}
• A byte, halfword or word load requires 1+w cycles in addition to the count listed in
• A doubleword load performs two memory accesses, so 2(1+w) cycles are needed in addition
• A byte, halfword or word store requires (1+w) cycles in addition to the count listed in
• A doubleword store performs two memory accesses, but these will be pipelined. The last of
where w is the number of wait states from the slave and bus system. The pipeline will stall
during these cycles.
to the count listed in
7, where w is the number of wait states from the slave and bus system. Stores to BOOT or
HSB can be performed in the background, so the pipeline will only stall if another memory
access is attempted during these w cycles. However, multiple stores to addresses in BOOT
or HSB can be automatically combined by the memory interface to create bursts on the HSB
bus. This means that any consecutive stores to BOOT or HSB sections will not stall the
pipeline unless the bus itself inserts wait cycles, for example due to wait states or bus
contention. Instructions not performing memory accesses will never stall the pipeline when
executed after stores to BOOT or HSB.
these accesses will stall if the instruction following the doubleword is a memory access
instruction other than a store to BOOT or HSB. Therefore, a non-memory instruction or
another store to BOOT or HSB should be scheduled after a doubleword store to BOOT or
HSB for maximum performance.
Load and store instructions
C
C
C
E
E
E
E
E
E
Operands
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rp[disp]
Table
8-7. The pipeline will stall during these cycles.
Description
Load unsigned byte with post-increment.
Load unsigned byte with pre-decrement.
Load unsigned byte with displacement.
Indexed Load unsigned byte.
Load unsigned byte with displacement if
condition satisfied. CPU revision 2 and higher
only.
Load signed byte with displacement.
Indexed Load signed byte.
Load signed byte with displacement if condition
satisfied. CPU revision 2 and higher only.
AVR32
Table
2
2
Issue
latency
IRAM
1
1
1
1
1
1
1
Table 8-
8-7,
78