AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 77
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
AT32UC3C2256C
Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2256C
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2256C-A2UR
Manufacturer:
Cirrus
Quantity:
48
Part Number:
AT32UC3C2256C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3C2256C-Z
Manufacturer:
ATMEL
Quantity:
261
Company:
Part Number:
AT32UC3C2256C-Z2UR
Manufacturer:
ATMEL
Quantity:
93
8.8
8.9
8.10
32002F–03/2010
Divide instructions
Saturate instructions
Load and store instructions
These instructions require several cycles in the EX stage to complete. The divs and divu instruc-
tions will be aborted immediately if any interrupts are pending, in order to limit the interrupt
latency. The divide instructions are faster in revision 2 than in revision 1 of the AVR32UC CPU.
Table 8-5.
1.) 35 cycles in revision 1 of the CPU
These instructions perform arithmetic operations with possible saturation.
Table 8-6.
This group includes all the load and store instructions. The address calculations are performed
by the adder in the EX stage. The EX adder also performs the writeback address calculation for
the autoincrement and autodecrement operation.
Loaded data are available at the end of the cycle in the EX stage. Byte and halfword data must
be extended and rotated before they are valid. This is performed in the EX stage. Ldins and
ldswp instructions also require modification in the EX stage before their results are valid. Stswp
instructions require modification before their data is output to the memory interface. This modifi-
cation is performed in the EX stage.
Mnemonics
divs
divu
Mnemonics
satadd.h
satadd.w
satsub.h
satsub.w
satrnds
satrndu
sats
satu
Divide instructions
Saturate instructions
E
E
E
E
E
E
E
E
E
E
E
Operands
Rd, Rx, Ry
Rd, Rx, Ry
Operands
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rs, imm
Rd >> sa, b5
Rd >> sa, b5
Rd >> sa, b5
Rd >> sa, b5
Description
Divide signed.
(32 ← 32/32)
(32 ← 32%32)
Divide unsigned.
(32 ← 32/32)
(32 ← 32%32)
Description
Saturated add halfwords.
Saturated add.
Saturated subtract halfwords.
Saturated subtract.
Signed saturate from bit given by sa after a
right shift with rounding of b5 bit positions.
Unsigned saturate from bit given by sa after a
right shift with rounding of b5 bit positions.
Shift sa positions and do signed saturate from
bit given by b5.
Shift sa positions and do unsigned saturate
from bit given by b5.
AVR32
Issue
latency
1
1
1
1
1
2
2
1
1
Issue
latency
19
19
1
1
77