AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 464

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.9.7
Name:
Access Type:
Offset:
Reset Value:
• BTF: Byte Transfer Finished
• REP: Repeated Start Received
• STO: Stop Received
• SMBDAM: SMBus Default Address Match
• SMBHHM: SMBus Host Header Address Match
• SMBALERTM: SMBus Alert Response Address Match
• GCM: General Call Match
• SAM: Slave Address Match
• BUSERR: Bus Error
32072G–11/2011
ORUN
BTF
31
23
15
7
-
-
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when byte transfer has completed.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a REPEATED START condition is received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the STOP condition is received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Default Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Host Header Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Alert Response Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the General Call Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the Slave Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced START or STOP condition has occurred.
Status Register
BUSERR
URUN
REP
30
22
14
6
-
SR
Read-only
0x18
0x000000002
SMBPECERR
STO
TRA
29
21
13
5
-
SMBTOUT
SMBDAM
28
20
12
4
-
-
SMBHHM
TCOMP
27
19
11
3
-
-
SMBALERTM
SEN
26
18
10
2
-
-
TXRDY
GCM
25
17
9
1
-
-
RXRDY
SAM
NAK
24
16
8
0
-
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