AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 451
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AT32UC3A3256AU
Manufacturer Part Number
AT32UC3A3256AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A0128AU.pdf
(2 pages)
5.AT32UC3A3128.pdf
(91 pages)
6.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256AU
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128AU PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- AT32UC3A3128 PDF datasheet #6
- Current page: 451 of 1012
- Download datasheet (16Mb)
Figure 22-8. Slave Transmitter with Multiple Data Bytes
Figure 22-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
22.8.4
32072G–11/2011
TCOMP
TXRDY
TWD
Slave Receiver Mode
Write THR (Data n)
NBYTES set to m
S
DADR
SR.NAK
SR.BTF
t
1
TWCK
: (CLK_TWIS period) x 2
TWD
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following is repeated:
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to
2. Receive a byte. Set SR.BTF when done.
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordi-
5. If STOP is received, SR.TCOMP will be set.
6. If REPEATED START is received, SR.REP will be set.
receive. This is necessary in order to know which of the received bytes is the PEC byte.
NBYTES can also be used to count the number of bytes received if using DMA.
NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is
used.
nary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC
is enabled and the last byte received was a PEC byte (indicated by NBYTES equal to
zero), The TWIS will automatically return an ACK if the PEC value was correct, other-
wise a NAK will be returned.
DATA (LSB)
R
A
Write THR (Data n+1)
DATA n
t
1
A
N
Write THR (Data n+m)
DATA n+5
Last data sent
t
1
A
P
DATA n+m
STOP sent by master
N
P
451
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