AT32UC3A0128 Atmel Corporation, AT32UC3A0128 Datasheet - Page 284

• Manufacturer Part Number: AT32UC3A0128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
25.9.6
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Transmit Frame Sync Length High part
The four MSB of the FSLEN bitfield.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSDEN: Frame Sync Data Enable
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1. Note: The four most significant bits fo this bitfield are in the FSLENHI bitfield.
FSDEN
MSBF
FSEDGE
0x6-0x7
31
23
15
FSOS
–
7
0x0
0x1
0x2
0x3
0x4
0x5
0x0
0x1
Transmit Frame Mode Register
Selected Transmit Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
30
22
14
TFMR
Read/Write
0x1C
0x00000000
–
6
–
FSLENHI
DATDEF
FSOS
29
21
13
–
5
28
20
12
–
4
27
19
11
–
3
DATLEN
26
18
10
–
2
FSLEN
DATNB
25
17
TX_FRAME_SYNC Pin
–
9
1
AT32UC3A
Undefined
Input-only
Output
Output
Output
Output
Output
FSEDGE
24
16
8
0
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