GS84032AT-100 GSI Technology, GS84032AT-100 Datasheet
GS84032AT-100
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GS84032AT-100 Summary of contents
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TQFP, BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • ...
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GS84018A 100-Pin TQFP Pinout 100 DDQ ...
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GS84032A 100-Pin TQFP Pinout 100 DDQ ...
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GS84036A 100-Pin TQFP Pinout 100 DDQ ...
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TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78 ...
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GS84018A Pad Out Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...
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GS84032A Pad Out Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...
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GS84036A Pad Out Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...
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BGA Pin Description Pin Location N4, P4 A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, R2, R6, T3 T2, T6 T2, T6 K7, K6, L7, L6, M6, N7, N6 H7, H6, G7, G6, F6, ...
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GS84018/32/36A Block Diagram Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version ...
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Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected ...
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Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
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Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E and that ADSP is ...
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Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...
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Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage on V Pins Voltage in V Pins DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V ...
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Undershoot Measurement and Timing 50% V -2.0V SS 20% tKC Capacitance 3 Parameter Control Input Capacitance Input Capacitance Output Capacitance ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current Output open Standby ZZ V – DD Current 0.2 V Device Deselected; Deselect All other inputs Current Rev: ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Clock ...
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Write Cycle Timing Single Write ADSP ADSC ADV –An 0 WR1 – Hi-Z DQ –DQ A ...
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Flow Through Read Cycle Timing Single Read ADSP ADSC ADV –An RD1 – tOLZ DQ ...
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Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0–An RD1 – tOE G tKQ Hi-Z DQ ...
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Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV –A RD1 – Hi-Z DQ –DQ A ...
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Pipelined SCD Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0–An RD1 – Hi-Z DQ –DQ A ...
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Sleep Mode Timing Diagram ADSP ADSC ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers ...
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GS84018/32/36A Output Driver Characteristics 60 Pull Down Drivers -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 3. Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ...
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TQFP Package Drawing Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e ...
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Package Dimensions—119-Pin BGA A Pin 1 Corner P N Top View Side View Rev: 1.12 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36AT/B-180/166/150/100 Bottom View Package Dimensions—119-Pin BGA ...
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... GS84018AT-166I 256K x 18 GS84018AT-150I 256K x 18 GS84018AT-100I 128K x 32 GS84032AT-180I 128K x 32 GS84032AT-166I 128K x 32 GS84032AT-150I 128K x 32 GS84032AT-100I 128K x 36 GS84036AT-180I 128K x 36 GS84036AT-166I 128K x 36 GS84036AT-150I 128K x 36 GS84036AT-100I 256K x 18 GS84018AB-180 256K x 18 GS84018AB-166 256K x 18 ...
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... GS84036AB-100I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. ...
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Revision History Types of Changes Rev. Code: Old; Format or Content New GS84018/32/36 Rev 1.02c 5/1999; GS84018/32/36A 1.00First Release 8/1999D GS84018/32/36A1.00 8/ 1999;GS84018/32/36A1.01 9/ 1999E GS84018/32/36A1.01 9/ 1999E;GS84018/32/36A1.02 GS84018/32/36A1.0210-11/ 1999;GS84018/32/36A1.032/ 2000G GS84018/32/36A1.032/2000G; 84018A_r1_04 84018A_r1_04; 84018A_r1_05 84018A_r1_05; 84018A_r1_06 84018A_r1_06; 84018A_r1_07 84018A_r1_07; ...