HM5212325FBPC-B60 HITACHI, HM5212325FBPC-B60 Datasheet
HM5212325FBPC-B60
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HM5212325FBPC-B60 Summary of contents
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... HM5212325FBPC-B60 128M LVTTL interface SDRAM Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word inputs and outputs are referred to the rising edge of the clock input packaged in standard 90-bump fine pitch BGA. Features Single chip wide bit solution ( 32) 3.3 V power supply ...
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... HM5212325FBPC-B60 2 variations of refresh Auto refresh Self refresh Full page burst length capability Sequential burst Burst stop capability Ordering Information Type No. Frequency HM5212325FBPC-B60* 100 MHz Note: 66 MHz operation at CAS latency = 2. 2 CAS latency Package bump FBGA (BP-90) ...
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... A7 A13 MB3 DQ31 SS V DQ30 V DQ29 DQ27 DQ28 SS V DQ26 V DQ25 DQ24 (Top view) HM5212325FBPC-B60 DQ0 CC CC DQ2 DQ1 SS DQ4 DQ3 CC DQ6 DQ5 NC DQ7 MB0 CS RAS NC NC A10 MB2 NC DQ16 CC DQ17 ...
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... HM5212325FBPC-B60 Pin Description Pin name A0 to A13 DQ0 to DQ31 CS RAS CAS WE DQMB0 to DQMB3 CLK CKE Open Note: 1. DQMB0: DQ0 to DQ7 DQMB1: DQ8 to DQ15 DQMB2: DQ16 to DQ23 DQMB3: DQ24 to DQ31 2. Don’t connect. Internally connected with die. 4 Function Address input ...
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... RAS CAS WE CLK CKE 4 DQMB 0 to DQMB Power-up Sequence and Initialization Sequence Power up sequence Low CKE, DQMB Low CLK Low CS, DQ 64-Mbit SDRAM Initialization sequence 100 s Power stabilize HM5212325FBPC-B60 64-Mbit SDRAM 200 s 5 ...
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... HM5212325FBPC-B60 Absolute Maximum Ratings Parameter Voltage on any pin relative to V Supply voltage relative Short circuit output current Operating temperature Storage temperature Note: 1. Respect Operating Conditions (Tcase = 0 to +70 C [Tj max = 110 C]) Parameter Supply voltage Input high voltage Input low voltage Notes: 1 ...
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... I — 135 CC4 I — 190 CC5 I — 2 CC6 I — 0.8 CC6 I – – 2.4 — — 0.4 OL HM5212325FBPC-B60 = Unit Test conditions Notes Burst length = min CKE = CKE = CKE ...
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... HM5212325FBPC-B60 Notes depends on output load condition when the device is selected output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. ...
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... DH t CEH t Trc Tras 50 RAS t Trcd 20 RCD t Trp Tdpl 10 DPL t Trrd 20 RRD — REF HM5212325FBPC-B60 = Max Unit Notes 1 — ns — ns — — — — — — ...
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... HM5212325FBPC-B60 Notes measurement assumes t 2. Access time is measured at 1.5 V. Load condition pF (min) defines the time at which the outputs achieves the low impedance state (max) defines the time at which the outputs achieves the high impedance state define CKE setup time to CLK rising edge except power down exit command ...
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... Package Dimensions HM5212325FBPC (BP-90) 10.0 Index 9.8 0. 0.20 90 0.08 Hitachi Code JEDEC EIAJ Mass (reference value) HM5212325FBPC-B60 Unit 0.8 B 2.4 5.6 0.45 0. Details of the part A BP-90 — — 0. ...
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... HM5212325FBPC-B60 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...
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... Package dimension Change tolerance value 0.2 Feb. 29, 2000 Capacitance C min min min: 2 min 1.0 May. 12 ,2000 Package dimension Change of seated height 6/6 to 3/3 A HM5212325FBPC-B60 Drawn by Approved by S. Hatano S. Hatano Y. Kagaya S. Hatano M. Nishimura I. Hihara 13 ...