HM5212325F Hitachi Semiconductor, HM5212325F Datasheet
HM5212325F
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HM5212325F Summary of contents
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... LVTTL interface SDRAM Description The Hitachi HM5212325F is a 128-Mbit SDRAM organized as 1048576-word and outputs are referred to the rising edge of the clock input packaged in standard 108 bump BGA. Features Single chip wide bit solution ( 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 1 ...
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... HM5212325F-B60 Full page burst length capability Sequential burst Burst stop capability Ordering Information Type No. Frequency HM5212325FBP-B60* 100 MHz Note: 66 MHz operation at CAS latency = 2. 2 CAS latency Package 108 bump BGA (BP-108) ...
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... CLK DQ MB0 NC NC DQ4 V SS DQ11 NC NC DQ5 V DQ10 DQ6 V DQ9 DQ7 V SS DQ8 (Top view) HM5212325F-B60 DQ16 NC NC DQ17 NC NC DQ18 NC NC DQ19 DQ NC MB2 RAS WE A10 A13 ...
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... HM5212325F-B60 Pin Description Pin name A0 to A13 DQ0 to DQ31 CS RAS CAS WE DQMB0 to DQMB3 CLK CKE Open Note: 1. DQMB0: DQ0 to DQ7 DQMB1: DQ8 to DQ15 DQMB2: DQ16 to DQ23 DQMB3: DQ24 to DQ31 2. Don’t connect. Internally connected with die. 4 Function Address input ...
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... RAS CAS WE CLK CKE 4 DQMB 0 to DQMB Power-up Sequence and Initialization Sequence Power up sequence Low CKE, DQMB Low CLK Low CS, DQ 64-Mbit SDRAM 100 s Power stabilize HM5212325F-B60 64-Mbit SDRAM Initialization sequence 200 s 5 ...
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... HM5212325F-B60 Absolute Maximum Ratings Parameter Voltage on any pin relative to V Supply voltage relative Short circuit output current Operating temperature Storage temperature Note: 1. Respect Operating Conditions (Tcase = 0 to +70 C [Tj max = 110 C]) Parameter Supply voltage Input high voltage Input low voltage Notes: 1 ...
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... I — 135 CC4 I — 190 CC5 I — 2 CC6 I — 0.8 CC6 I – – 2.4 — — 0.4 OL HM5212325F-B60 = Unit Test conditions Notes Burst length = min CKE = CKE = CKE ...
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... HM5212325F-B60 Notes depends on output load condition when the device is selected output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. ...
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... DH t CEH t Trc Tras 50 RAS t Trcd 20 RCD t Trp Tdpl 10 DPL t Trrd 20 RRD — REF HM5212325F-B60 = Max Unit Notes 1 — ns — ns — — — — — — ...
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... HM5212325F-B60 Notes measurement assumes t 2. Access time is measured at 1.5 V. Load condition pF (min) defines the time at which the outputs achieves the low impedance state (max) defines the time at which the outputs achieves the high impedance state define CKE setup time to CLK rising edge except power down exit command ...
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... Package Dimensions HM5212325FBP Series (BP-108) Preliminary 4 C1.2 Pin 1 Index -B- 108 0.75 0.30 M 0.15 M 14.00 -A- 13.0 0. Details of the part A HM5212325F-B60 1.27 Hitachi Code BP-108 JEDEC — EIAJ — Weight (reference value) 1.2 g Unit ...
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... HM5212325F-B60 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...
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... I3 C min max: 6 Characteristics Addition of t Addition of t Package dimension Change tolerance of height max (CL = 2): 100 mA CC1 max (CL = 2): 110 mA CC4 min ( max ( HM5212325F-B60 Drawn by Approved by S. Hatano S. Hatano 13 ...