STA529Q STMicroelectronics, STA529Q Datasheet - Page 21

• Manufacturer Part Number: STA529Q
• Description: IC AMP 2X100MW CLASS D 52VFQFPN
• Manufacturer: STMicroelectronics
• Series: Sound Terminal™r
• Type: Class Dr

Specifications of STA529Q

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 100mW x 2 @ 16 Ohm
• Voltage - Supply: 1.5 V ~ 1.95 V
• Features: Depop, I²C, I²S, Mute, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 52-VFQFN, 52-VFQFPN
• Ic Function: FFX Audio Codec Analogue & Digital Inputs, Class D Amplifier
• Brief Features: Up To 96dB Dynamic Range, FFX Class-D Driver
• Supply Voltage Range: 1.55V To 1.95V, 1.8V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8879

STA529
6.2
Configuration examples
The STA529 PLL can be configured in two ways:
The default startup configuration reads the device defaults. With this configuration, it is not
necessary to program the PLL dividers directly as preset values are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined by the following equations.
Output division factor:
Relation between input and output clock frequency:
If register bit PLLCFG0.FRAC_CTRL = 1
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/2
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
If register bit PLLCFG0.FRAC_CTRL = 0, then:
In the above equations:
When selecting the values for IDF, LDF and FRACT, ensure that the following limits are
maintained:
There are also some additional constraints on IDF and LDF. IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
default startup configuration
direct PLL programming
ODF = 2.
f
f
f
f
f
FRACT = decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = input division factor
LDF = loop division factor
ODF = output division factor = 2
f
f
f
f
2.048 MHz < f
2.048 MHz < f
65.536 MHz < f
INFIN
VCO
PHI
VCO
PHI
INFIN
XTI
VCO
PHI
= XTI frequency
= f
= f
= frequency of the PLL output clock.
= f
= f
= VCO frequency
= f
= INFIN frequency
VCO
VCO
INFIN
INFIN
XTI
/ ODF.
/ ODF.
/ IDF.
* (LDF + FRACT / 2
* LDF
XTI
INFIN
VCO
< 49.152 MHz
< 16.384 MHz
< 98.304 MHz
Doc ID 13095 Rev 2
16
+ 1 / 2
17
)
17
factor is not in the
21/55
PLL