STA529Q STMicroelectronics, STA529Q Datasheet - Page 20

• Manufacturer Part Number: STA529Q
• Description: IC AMP 2X100MW CLASS D 52VFQFPN
• Manufacturer: STMicroelectronics
• Series: Sound Terminal™r
• Type: Class Dr

Specifications of STA529Q

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 100mW x 2 @ 16 Ohm
• Voltage - Supply: 1.5 V ~ 1.95 V
• Features: Depop, I²C, I²S, Mute, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 52-VFQFN, 52-VFQFPN
• Ic Function: FFX Audio Codec Analogue & Digital Inputs, Class D Amplifier
• Brief Features: Up To 96dB Dynamic Range, FFX Class-D Driver
• Supply Voltage Range: 1.55V To 1.95V, 1.8V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8879

PLL
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Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division
factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing f
division factor (LDF). The output of this block is clock FBCLK.
Output frequency divider
The output frequency divider divides f
output clock PHI and the clock to the core. In the STA529, ODF = 2 and cannot be
reconfigured.
Lock-detect circuit
The output of this block (signal LOCKP) is asserted high when the PLL enters the state of
Coarse Lock in which the output frequency is within ±10%, approximately, of the desired
frequency. LOCKP is refreshed every 32 cycles of clock INFIN. The generated value is
based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN
cycles. The different cases generated after comparison are as follows.
PLL filter
Figure 6
C1 = 250 pF and C2 = 82 pF.
Figure 6.
Table 12 on page 15
If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number
of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP
stays at 0.
If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number
of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17,
otherwise LOCKP stays at 1.
If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP
stays at 1. In this case, the PLL is unlocked.
below shows the PLL filter circuit. Recommended values are R1 = 12.5 kΩ,
PLL filter circuit
gives a typical lock time value for the PLL.
C1
R1
Doc ID 13095 Rev 2
VCO
Ground
by the output division factor (ODF) to produce the
Vc
C2
VCO
by a factor called the loop
STA529