SAB-C161K-LM Infineon Technologies AG, SAB-C161K-LM Datasheet
SAB-C161K-LM
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... Edition 2001-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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C161K/O Revision History: 2001-01 Previous Version: 03.97 09.96 Page Subjects (major changes since last revision) All Converted to Infineon layout All C161V removed 2 Ordering Codes and Cross-Reference replaced with Derivative Synopsis Open drain functionality described for ...
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Single-Chip Microcontroller C166 Family C161K/O • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division ( bit) ...
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... C161K/O Derivative Synopsis 1) Derivative Max. Oper. Frequency SAF-C161K-LM 20 MHz SAB-C161K-LM 20 MHz SAF-C161K-L25M 25 MHz SAB-C161K-L25M 25 MHz SAF-C161K-LM3V 20 MHz SAB-C161K-LM3V 20 MHz SAF-C161O-LM 20 MHz SAB-C161O-LM 20 MHz SAF-C161O-L25M 25 MHz SAB-C161O-L25M 25 MHz SAF-C161O-LM3V 20 MHz SAB-C161O-LM3V 20 MHz 1) This Data Sheet is valid for devices starting with and including design step HA. ...
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Introduction The C161K derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with peripheral functionality and enhanced IO-capabilities. The C161K/O is especially suited ...
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Pin Configuration MQFP Package (top view XTAL1 2 XTAL2 P3.2/CAPIN 5 P3.3/T3OUT 6 P3.4/T3EUD 7 P3.5/T4IN 8 P3.6/T3IN 9 P3.7/T2IN 10 P3.8/MRST 11 P3.9/MTSR 12 P3.10/TxD0 13 P3.11/RxD0 14 P3.12/BHE/WRH 15 P3.13/SCLK 16 ...
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Table 2 Pin Definitions and Functions Symbol Pin Input Function Num Outp. XTAL1 2 I XTAL1: XTAL2 3 O XTAL2: To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num Outp External Memory Read Strobe activated for every external instruction or data read access. WR External Memory Write Strobe. In WR-mode ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num Outp. RSTIN 65 I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C161K/O. An internal pullup resistor permits ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Function Num Outp Port 7-bit bidirectional I/O port bit-wise programmable for input or output via direction bits. For a pin configured as input, ...
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Functional Description The architecture of the C161K/O combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...
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... MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C161K/O is prepared to incorporate on-chip program memory (not in the ROM-less derivatives, of course) for code or constant data. The internal ROM area can be mapped either to segment 0 or segment 1 ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...
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The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...
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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C161K/O is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
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Table 3 C161K/O Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag External Interrupt 1 CC9IR External Interrupt 2 CC10IR External Interrupt 3 CC11IR External Interrupt 4 CC12IR External Interrupt 5 CC13IR External Interrupt 6 CC14IR External Interrupt ...
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The C161K/O also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T2EUD CPU Control T2IN CPU T3IN Control T3EUD T4IN Control CPU T4EUD … 10 Figure 5 Block Diagram of GPT1 With its ...
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The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. Note: Block GPT2 is only available in the ...
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...
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... Parallel Ports The C161K/O provides I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...
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... BAND, BOR, AND/OR/XOR direct bit with direct bit BXOR BCMP Compare direct bit to direct bit BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 ...
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... Software Reset IDLE Enter Idle Mode PWRDN Enter Power Down Mode (supposes NMI-pin being low) SRVWDT Service Watchdog Timer DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence ...
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... The following table lists all SFRs which are implemented in the C161K/O in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “ ...
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Table 6 C161K/O Registers, Ordered by Name (cont’d) Name Physical Address DP0H b F102 DP0L b F100 DP1H b F106 DP1L b F104 DP2 b FFC2 H DP3 ...
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Table 6 C161K/O Registers, Ordered by Name (cont’d) Name Physical Address P3 b FFC4 FFC8 FFA2 FFCC H PECC0 FEC0 H PECC1 FEC2 H PECC2 FEC4 H PECC3 FEC6 H PECC4 ...
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Table 6 C161K/O Registers, Ordered by Name (cont’d) Name Physical Address SSCEIC b FF76 H SSCRB F0B2 SSCRIC b FF74 H SSCTB F0B0 SSCTIC b FF72 H STKOV FE14 H STKUN FE16 H SYSCON ...
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Absolute Maximum Ratings Table 7 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature Voltage on V pins with DD respect to ground ( Voltage on any pin with respect to ground ( Input ...
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... V). The absolute sum of input overload C161K C161O Unit Notes V Active mode MHz f CPUmax V Power Down mode V Active mode MHz CPUmax V Power Down mode V Reference voltage 2)3) mA Per pin – ° C SAB-C161K/O … ° C SAF-C161K/O … ° C SAK-C161K/O … V2.0, 2001-01 ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161K/ O and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
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DC Characteristics (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) Parameter 4) RSTIN active current 7) RD/WR inact. current 7) RD/WR active current 7) ALE inactive current 7) ALE active current 7) Port 6 inactive current 7) Port 6 active ...
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DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL, all except RSTIN and XTAL1) Input high voltage RSTIN (when operated as input) Input high ...
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DC Characteristics (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) Parameter PORT0 configuration current XTAL1 input current 8) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal ...
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Power Consumption C161K/O (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Power-down mode supply current 1) The supply current is a function of the ...
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I mA 100 Figure 7 Supply/Idle Current as a Function of Operating Frequency Data Sheet C161K C161O I DD5max I DD5typ I DD3max I DD3typ I IDX5max I IDX3max ...
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AC Characteristics Definition of Internal Timing The internal operation of the C161K/O is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external ...
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Table 9 C161K/O Clock Generation Modes CLKCFG CPU Frequency (P0H.7- × F CPU OSC × 1 OSC OSC 1) The maximum frequency depends on the duty cycle ...
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AC Characteristics Table 10 External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Oscillator period OSC 1) High time Low time Rise time ...
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V DD Figure 9 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 40 MHz strongly recommended to ...
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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at Figure 10 Input Output Waveforms V + 0.1 V ...
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Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 12 ...
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Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 t Parameter Symbol RD, WR low time t (no RW-delay valid data in t (with RW-delay valid data ...
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Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 t Parameter Symbol Address float after RdCS, t WrCS (with RW delay) Address float after RdCS, t WrCS (no RW delay) RdCS ...
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AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 t Parameter Symbol ALE high time t Address setup to ALE t Address hold after ALE t ALE falling edge to ...
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Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 t Parameter Symbol Data float after RD t Data valid Data hold after WR t ALE rising edge after ...
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Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 t Parameter Symbol Data valid to WrCS t Data hold after RdCS t Data float after RdCS t Address hold after t ...
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ALE CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 12 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE t 38 CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 13 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet t 16 ...
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ALE CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 14 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE t 38 CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 15 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet t 16 ...
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AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 t Parameter Symbol ALE high time t 5 Address setup to ALE t 6 ALE falling edge to RD ...
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Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 t Parameter Symbol Data valid Data hold after ALE rising edge after t 26 RD, ...
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Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 t Parameter Symbol Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address ...
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AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 t Parameter Symbol ALE high time t 5 Address setup to ALE t 6 ALE falling edge to RD ...
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Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 t Parameter Symbol Data valid Data hold after ALE rising edge after t 26 RD, ...
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Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 t Parameter Symbol Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address ...
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ALE CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE t 38 CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE ...
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ALE CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE t 38 CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE ...
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Package Outlines P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.65 0.3 ±0. Index Marking 0.6x45˚ 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc. ...
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