CY7C1356A-200AC Cypress Semiconductor Corporation., CY7C1356A-200AC Datasheet

CY7C1356A-200AC

Manufacturer Part Number

CY7C1356A-200AC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

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Cypress Semiconductor Corporation

Document #: 38-05161 Rev. *B

Features

Functional Description

The

GVT71512ZC18 SRAMs are designed to eliminate dead

cycles when transitioning from Read to Write or vice versa.

These SRAMs are optimized for 100% bus utilization and

achieve Zero Bus Latency

(NoBL ). They integrate 262,144 × 36 and 524,288 × 18

SRAM cells, respectively, with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. These employ high-speed, low-power CMOS

designs using advanced triple-layer polysilicon, double-layer

metal technology. Each memory cell consists of four

transistors and two high-valued resistors.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current Commercial

• Zero Bus Latency, no dead cycles between Write and

• Fast clock speed: 200, 166, 133, 100 MHz

• Fast access time: 3.2, 3.6, 4.2, 5.0 ns

• Internally synchronized registered outputs eliminate

• Single 3.3V –5% and +5% power supply V

• Separate V

• Single WEN (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

• Interleaved or linear four-word burst capability

• Individual byte Write (BWa–BWd) control (may be tied

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

•Automatic power-down feature available using ZZ mode

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid

Read cycles

the need to control OE

control signal registers for fully pipelined applications

LOW)

or CE select

Array), and 100-pin TQFP packages

CY7C1354A/GVT71256ZC36

CCQ

for 3.3V or 2.5V I/O

(ZBL )/No Bus Latency

Commercial

and

•

3901 North First Street

CY7C1356A/

256K x 36/512K x 18 Pipelined SRAM

7C1354A-200

7C1356A-200

71256ZC36-5

71512ZC18-5

560

3.2

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE, CE

Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,

and BWd), and Read-Write Control (WEN). BWc and BWd

apply to CY7C1354A/GVT71256ZC36 only.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either Read or Write.

A clock enable (CEN) pin allows operation of the

CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18

to be suspended as long as necessary. All synchronous inputs

are ignored when (CEN) is HIGH and the internal device

registers will hold their previous values.

There are three chip enable pins (CE, CE

user to deselect the device when desired. If any one of these

three are not active when ADV/LD is LOW, no new memory

operation can be initiated and any burst cycle in progress is

stopped. However, any pending data transfers (Read or Write)

will be completed. The data bus will be in high-impedance

state two cycles after chip is deselected or a Write cycle is

initiated.

The

GVT71512ZC18 have an on-chip two-bit burst counter. In the

burst

CY7C1356A/GVT71512ZC18 provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the MODE input pin. The MODE pin

selects between linear and interleaved burst sequence. The

ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH)

Output Enable (OE), Sleep Enable (ZZ) and burst sequence

select (MODE) are the asynchronous signals. OE can be used

to disable the outputs at any given time. ZZ may be tied to

LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

7C1354A-166

7C1356A-166

71256ZC36-6

71512ZC18-6

CY7C1354A/GVT71256ZC36

•

mode,

480

3.6

with NoBL™ Architecture

San Jose

CY7C1354A/GVT71256ZC36

CY7C1356A/GVT71512ZC18

the

71256ZC36-7.5

71512ZC18-7.5

7C1354A-133

7C1356A-133

, and CE

CY7C1354A/GVT71256ZC36

•

410

4.2

CA 95134

), Cycle Start Input (ADV/LD),

Revised April 25, 2002

71256ZC36-10

71512ZC18-10

7C1354A-100

7C1356A-100

and

, CE

•

350

5.0

408-943-2600

) that allow the

CY7C1356A/

Unit

and

Related parts for CY7C1356A-200AC

CY7C1356A-200AC Summary of contents

Page 1

... The CY7C1354A/GVT71256ZC36 GVT71512ZC18 have an on-chip two-bit burst counter. In the burst mode, CY7C1356A/GVT71512ZC18 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin and CY7C1356A/ selects between linear and interleaved burst sequence. The ...

Page 2

... CEN A0, A1, A CLK OE# OE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 [1] Address Control Input Registers Control Logic Mux Output Registers Output Buffers DQa-DQd ...

Page 3

... DQa 28 53 DQa DQa DQa 74 DQa 73 DQa DQa 69 DQa 68 CY7C1356A (512K × 18) 64 DQa 63 DQa DQa 59 DQa Page ...

Page 4

... DQc E DQc F V CCQ G DQc H DQc J V CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CY7C1356A/GVT71512ZC18 (512K × 18)–7 × 17 BGA CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb ...

Page 5

... MODE is a static DC input. Input- Sleep Enable: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Pin Description are used with used with CE and CE 2 ...

Page 6

... The effect of CEN sampled HIGH on the device outputs the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Pin Description or to GND. CC Pin Description ...

Page 7

... ADV/ Read or Write operation. The data bus activity for the current cycle takes place two clock cycles later. Input- Clock: This is the clock input to CY7C1356A/GVT71512ZC18. Except Synchronous for OE, ZZ, and MODE, all timing references for the device are made with respect to the rising edge of CLK. ...

Page 8

... V Fourth First Address Address [5] (internal) (external) A...A A... A...A A... A...A A... A...A A... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Pin Description or to GND. CC [4] BWa BWb BWc ...

Page 9

... L L Write Next External L L Write Next are all True. 3 HIGH means are HIGH CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Min. Max. – 0. – 0. CYC 2t CYC CE CEN BWx OE (2 cycles later ...

Page 10

... TDI and TDO. TDO is connected to the LSB of any register (see Figure 2). Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (V for five rising edges of TCK and pre-loads the instruction register with the IDCODE command ...

Page 11

... The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state ...

Page 12

... TMS at the rising edge of TCK. Document #: 38-05161 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [21] Page ...

Page 13

... A OHC [23 8.0 mA OLT [23 8.0 mA OHT /2; undershoot: V (AC) <–0.5V for t < t KHKH IL KHKH must not exceed V . Control input signals (such as WEN and ADV/LD) may not have pulse widths less than CC CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 0 Selection Circuitry [22] Min. Max. 2 0.3 CC –0.3 0.8 – ...

Page 14

... CS CH 27. Test conditions are specified using the load in TAP AC test conditions. Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 [26, 27] Over the Operating Range Description Min. Max. Unit 20 ...

Page 15

... XXXXXX XXXXXX 00011100100 00011100100 1 1 Bit Size (x18 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ALL INPUT PULSES 3.0V 1.5V 1 TLTH Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. ...

Page 16

... Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description Page ...

Page 17

... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump BWa 93 BWb 94 BWc 95 BWd 100 DQc 1 DQc 2 DQc 3 DQc 6 DQc 7 DQc 8 ...

Page 18

... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump ID CLK BWa 93 BWb 100 DQb 8 DQb 9 DQb 12 DQb DQb 18 DQb 19 ...

Page 19

... Device deselected; all inputs < > MAX CLK cycle time > t Min. KC < –2.0V for t < means no input lines are changing. CYC CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 [28] Ambient Temperature +70 C 3. +85 C Min. Max. 2 0.3 CC 2.0 1.7 –0.3 0.8 – ...

Page 20

... KQHZ KQLZ OEHZ CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Typ. Max 6.5 TQFP Typ ALL INPUT PULSES 90% 90% 10% 10% 1.0 ns (c) -6/ -7.5/ -10/ 133 MHz 100 MHz Max. Min. Max. Min. Max. 7.5 10 2.6 3 ...

Page 21

... etc., where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the 2 is HIGH. 2 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 (Burst Wraps around (CKE# HIGH , eliminates to initial state) current L-H clock edge) Q(A +2) Q(A +3) ...

Page 22

... Pipeline Write ) represents the first input to the external address etc., where address bits A0 and A1 are advancing for the four-word burst in the sequence defined by the state of 2 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 BW (CKE# HIGH , eliminates (Burst Wraps around current L-H clock edge) to initial state) ...

Page 23

... Document #: 38-05161 Rev BW KQHZ KQLZ KQX Q Read D Write Write . D(A ) represents the input data to the SRAM corresponding to address CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Q(A ) Q(A 6 Read D Page ...

Page 24

... L-H clock transition did not occur. All internal registers in the SRAM will retain their previous states. Document #: 38-05161 Rev KQHZ Q KQLZ CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 KQX D Page Q ...

Page 25

... Q KQX D(A ) represents the input data to the SRAM corresponding to address sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one 2 3 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 OEHZ Q D etc. 3 Page ...

Page 26

... I/Os Notes: 50.Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 51. I/Os are in three-state when exiting ZZ sleep mode Document #: 38-05161 Rev ZZS I (active DDZZ Three-state CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 t ZZREC Page ...

Page 27

... GVT71256ZC36-5 CY7C1354A-200BGC/ GVT71256ZC36B-5 166 CY7C1354A-166AC/ GVT71256ZC36-6 CY7C1354A-166BGC/ GVT71256ZC36B-6 133 CY7C1354A-133AC/ GVT71256ZC36-7.5 CY7C1354A-133BGC/ GVT71256ZC36B-7.5 100 CY7C1354A-100AC/ GVT71256ZC36-10 CY7C1354A-100BGC/ GVT71256ZC36B-10 200 CY7C1356A-200AC/ GVT71512ZC18-5 CY7C1356A-200BGC/ GVT71512ZC18B-5 166 CY7C1356A-166AC/ GVT71512ZC18-6 CY7C1356A-166BGC/ GVT71512ZC18B-6 133 CY7C1356A-133AC/ GVT71512ZC18-7.5 CY7C1356A-133BGC/ GVT71512ZC18B-7.5 100 CY7C1356A-100AC/ GVT71512ZC18-10 CY7C1356A-100BGC/ GVT71512ZC18B-10 Document #: 38-05161 Rev. *B ...

Page 28

... Speed (MHz) Ordering Code 166 CY7C1354A-166ACI/ GVT71256ZC36-6 CY7C1354A-166BGCI/ GVT71256ZC36B-6I 133 CY7C1354A-133ACI/ GVT71256ZC36-7.5I CY7C1354A-133BGCI/ GVT71256ZC36B-7.5I 100 CY7C1354A-100ACI/ GVT71256ZC36-10I CY7C1354A-100BGCI/ GVT71256ZC36B-10I 200 CY7C1356A-200ACI/ GVT71512ZC18-5I CY7C1356A-200BGCI/ GVT71512ZC18B-5I 166 CY7C1356A-166ACI/ GVT71512ZC18-6I CY7C1356A-166BGCI/ GVT71512ZC18B-6I 133 CY7C1356A-133ACI/ GVT71512ZC18-7.5I CY7C1356A-133BGCI/ GVT71512ZC18B-7.5I 100 CY7C1356A-100ACI GVT71512ZC18-10I CY7C1356A-100BGCI/ GVT71512ZC18B-10I Document #: 38-05161 Rev. *B ...

Page 29

... Package Diagrams 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 51-85050-A Page ...

Page 30

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 119-Lead BGA ( 2.4) BG119 51-85115-*A ...

Page 31

... Document Title: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05161 Issue REV. ECN No. Date ** 3000 4/21/00 *A 114095 03/12/02 *B 114095 05/30/02 Document #: 38-05161 Rev. *B Orig. of Change Description of Change CXV New Data Sheet GLC 1) Updated separate GLC 1) Added “I” temp 2) Added automatic power down to features ...

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