MAX9888EWY+T Maxim Integrated Products, MAX9888EWY+T Datasheet - Page 52

• Manufacturer Part Number: MAX9888EWY+T
• Description: IC CODEC AUDIO FLEXSOUND 63WLP
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive®, FLEXSOUND™r
• Type: Class Dr

Specifications of MAX9888EWY+T

• Output Type: 3-Channel with Stereo Headphones
• Max Output Power X Channels @ Load: 1.37W x 2 @ 8 Ohm; 40mW x 2 @ 16 Ohm
• Voltage - Supply: 2.8 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²S, Microphone, Mute, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 63-WLP
• For Use With: MAX9888EVKIT+ - KIT EVALUATION FOR MAX9888
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio CODEC
with FLEXSOUND Technology
52
PIN
G1
G2
G3
G4
G5
G6
G7
G8
G9
E1
E2
E4
E5
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
DIGMICDATA
DIGMICCLK
SDOUTS1
SDOUTS2
EXTMICP
LRCLKS2
DVDDS1
DVDDS2
MICBIAS
BCLKS2
MIC1N/
SDINS2
MIC1P/
MIC2N
MIC2P
NAME
DGND
AGND
MCLK
DVDD
AVDD
PREG
INA1/
SDA
REG
SCL
IRQ
REF
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00
change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ
until it is cleared by reading the I
full output swing.
Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
be retasked as a digital microphone data input.
Single-Ended Line Input A1. Also negative differential line input A or positive differential external
microphone input.
Digital Ground
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an
output when in master mode. The input/output voltage is referenced to DVDDS2.
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and
determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is
a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master
mode. The input/output voltage is referenced to DVDDS2.
I
I
Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
Converter Reference. Bypass to AGND with a 2.2FF capacitor.
Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
be retasked as a digital microphone clock output.
Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2.
S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2.
Digital Power Supply. Supply for the digital core and I
capacitor.
Analog Power Supply. Bypass to AGND with a 1FF capacitor.
Positive Internal Regulated Supply. Bypass to AGND with a 1FF capacitor.
Analog Ground
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external resistor in the 2.2kI to 1kI
range should be used to set the microphone current.
Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
2
2
C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
C Serial-Clock Input
2
C status register 0x00. Connect a 10kI pullup resistor to DVDD for
FUNCTION
Pin Description (continued)
2
C interface. Bypass to DGND with a 1FF