TDF8599TD/N2,512 NXP Semiconductors, TDF8599TD/N2,512 Datasheet
TDF8599TD/N2,512
Specifications of TDF8599TD/N2,512
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TDF8599TD/N2,512 Summary of contents
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TDF8599 2 I C-bus controlled dual channel 43 W/2 85 W/1 Rev. 02 — 30 July 2009 1. General description The TDF8599 is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an NDMOST-NDMOST output stage based on SOI BCDMOS ...
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... NXP Semiconductors C-bus mode load detection N AC load detection N Thermal pre-warning diagnostic level setting N Identification of activated protections or warnings N Selectable diagnostic information available using pin DIAG and pin CLIP I Qualified in accordance with AEC-Q100 3. Applications I Car audio 4. Quick reference data Table 1. ...
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... NXP Semiconductors 6. Block diagram SEL_MUTE Fig 1. TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier V DDA 9 AGND 8 SVRR TDF8599 CONTROL 1 IN1P 2 IN1N CONTROL 5 ACGND + CONTROL 3 IN2P 4 IN2N CONTROL 18 OSCSET 19 OSCIO OSCILLATOR 17 SSM 12 MOD STABI DDD MODE 16 SELECT ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier 36 GNDD/ DDD VSTAB1 34 OUT1N 33 32 BOOT1N PGND1 30 29 BOOT1P 28 OUT1P TDF8599TH OUT2P 27 BOOT2P 26 25 PGND2 BOOT2N 23 OUT2N 22 21 VSTAB2 DCP 20 OSCIO 19 Heatsink up (top view) pin confi ...
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... NXP Semiconductors Fig 3. 7.2 Pin description Table 3. Symbol IN1P IN1N IN2P IN2N ACGND EN SEL_MUTE SVRR AGND V DDA ADS MOD TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier IN1P 1 2 IN1N IN2P 3 4 IN2N ACGND SEL_MUTE SVRR ...
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... NXP Semiconductors Table 3. Symbol CLIP DIAG SDA SCL SSM OSCSET OSCIO DCP VSTAB2 OUT2N BOOT2N [ PGND2 BOOT2P OUT2P OUT1P BOOT1P PGND1 [ BOOT1N OUT1N VSTAB1 V DDD GNDD/HW [ input output, I/O = input/output ground and P = power supply. [2] In this data sheet supply voltage V 8. Functional description 8.1 General The TDF8599 is a dual full bridge (BTL) audio power amplifi ...
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... NXP Semiconductors The TDF8599 includes integrated common circuits for all channels such as the oscillator, all reference sources, mode functionality and a digital timing manager. In addition, the built-in protection includes thermal foldback, temperature, overcurrent and overvoltage (load dump). The TDF8599 operates in either I DC load detection, frequency hopping and extended configuration functions are provided together with enhanced diagnostic information ...
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... NXP Semiconductors Table 4. Pin EN HIGH (S2 closed) LOW (S2 open) [ not care. Table 5. Pin EN HIGH (S2 closed) LOW (S2 open) [ not care. 8.3 Pulse-width modulation frequency The output signal from the amplifi PWM signal with a clock frequency of f frequency is set by connecting a resistor (R optimal clock frequency setting is between 300 kHz and 400 kHz. Connecting a resistor ...
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... NXP Semiconductors The value of the resistor osc Fig 5. Fig 6. In Master mode, Spread spectrum mode and frequency hopping can be enabled. In Slave mode, phase staggering and phase lock operation can be selected. An external clock can be used as the master-clock on pin OSCIO of the slave devices. When using an external ...
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... NXP Semiconductors The spread spectrum frequency (f f SSM where the voltage on pin OSCSET = SSM 100 A a. Off Fig 7. The frequency swings between 0.95 OSCIO max(V) SSM min(V) Fig 8. Spread spectrum operation in Master mode 8.3.3 Frequency hopping (Master mode) Frequency hopping is a technique used to change the oscillator frequency for AM tuner compatibility ...
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... NXP Semiconductors Connecting pin SSM to pin AGND disables phase lock operation and causes the slave to directly use the external oscillator signal. Values for C the desired loop bandwidth (B corresponding values for C C PLL_p Remark: C more detailed information. C PLL_s When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled, the PLL loop bandwidth B a ...
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... NXP Semiconductors 2 In non modulation (see Parallel mode operation (see C-bus mode, pin MOD can only select Parallel mode. In addition, the modulation mode and phase shift are programmed using I Table MOD 0 (short to AGND) 4 100 (open) [1] See Section 8.4.3 on page 14 The information on pin MOD is latched when one of the TDF8599 outputs starts switching, to avoid incorrect information on pin MOD caused by disturbances of switching amplifi ...
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... NXP Semiconductors a. Bridge half 1 b. Bridge half 2 switched in the opposite phase to bridge half 1 Fig 11. AD modulation a. Phase switching cycle b. Inverted signal to the modulator Fig 12. BD modulation 8.4.2 Phase staggering (Slave mode) In Slave mode with phase lock operation enabled, a phase shift with respect to the incoming clock signal can be selected to distribute the switching moments over time ...
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... NXP Semiconductors Fig 13. Master and slave operation with 8.4.3 Parallel mode In Parallel mode; the two output stages operate in parallel to enlarge the drive capability. The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board (PCB) as shown in as shown in Fig 14. Parallel mode ...
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... NXP Semiconductors Table 9. Protection type Thermal foldback Overtemperature Overcurrent Window DC Offset Undervoltage Overvoltage 8.5.1 Thermal foldback Thermal Foldback Protection (TFP) is activated when the average junction temperature exceeds the threshold level (145 C). TFP decreases amplifier gain such that the combination of power dissipation and R threshold level ...
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... NXP Semiconductors 8.5.4 Window protection Window Protection (WP) checks the PWM output voltage before switching from Standby mode to Mute mode (with both outputs switching) and is activated as follows: • During the start-up sequence: – When the TDF8599 is switched from standby to mute (t circuit on one of the output terminals (i.e. between V start-up procedure is interrupted and the TDF8599 waits for open circuit outputs. No large currents fl ...
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... NXP Semiconductors C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts down both channels when bit IB2[D7] is not set. To restart the TDF8599 must be toggled or DCP disabled by connecting pin DCP to pin AGND ...
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... NXP Semiconductors 8.6 Diagnostic output 8.6.1 Diagnostic table The diagnostic information for I The instruction bitmap and data bytes are described in Pins DIAG and CLIP have an open-drain output which must have an external pull-up resistor connected to an external voltage. Pins CLIP and DIAG can show both fixed and ...
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... NXP Semiconductors 8.6.2 Load identification (I 8.6.2.1 DC load detection DC load detection is only available in I The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load detection is enabled when bit IB2[D2 Load detection takes place before the class-D amplifier output stage starts switching in Mute mode and the start-up time from Standby mode to Mute mode is increased by t Fig 17 ...
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... NXP Semiconductors Remark: DC load detection identifies a short circuited speaker as a valid speaker load. OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2, performs diagnostics on shorted loads. However, the diagnostics are performed after the DC load detection cycle has finished and once the amplifi Operating mode. ...
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... NXP Semiconductors IB1[D0 IB2[D2 IB1[D1 IB2[D1 DB1[D4 DB2[D4 DB1[D6 IB1[D0 IB2[D2 IB1[D1 IB2[D1 Fig 20. Recommended start-up sequence with DC load detection enabled 8.6.2.3 AC load detection AC load detection is only available in I The default setting for bit IB3[D4 disables AC load detection. When AC load detection is enabled (bit IB3[D4] = 1), the amplifi ...
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... NXP Semiconductors 8.6.2.4 CLIP detection CLIP detection gives information for clip levels the clip detection circuitry on both channel 1 and channel 2. Setting either bit IB1[D5] or bit IB2[D5] to logic 0 defines which channel reports clip information on the CLIP pin. In Parallel mode, disabling clip detection on both channels requires both bits to be set to bit IB1[D5 and bit IB2[D5 ...
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... NXP Semiconductors V DDA DIAG EN ACGND IB1[D0] and IB2[D0 SEL_MUTE SVRR t t wake d(stb-mute) OUTn (1) Shutdown hold delay. (2) Master mode shutdown delay. (3) Shutdown delay. Fig 21. Start-up and shutdown timing in I TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier ...
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... NXP Semiconductors V DDA DIAG EN ACGND SEL_MUTE SVRR OUTn (1) Shutdown hold delay. (2) Shutdown delay. (3) Master mode shutdown delay. Fig 22. Start-up and shutdown timing in non C-bus specification TDF8599 address with hardware address select. Table 13. [1] R ADS Open 100 k to pin AGND pin AGND pin AGND 4 ...
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... NXP Semiconductors SCL SDA M p START (1) SLAVE (1) When SCL is HIGH, SDA changes to form the start or stop condition. 2 Fig 23. I C-bus start and stop conditions SCL 1 2 MSB MSB 1 SDA M p START ADDRESS SLAVE (1) To stop the transfer after the last acknowledge a stop condition must be generated. ...
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... NXP Semiconductors 9.1 Instruction bytes If R/W bit = 0, the TDF8599 expects three instruction bytes: IB1, IB2 and IB3. After a power-on reset, all unspecified instruction bits must be set to zero’. Table 14. Instruction byte descriptions Bit Value Description Instruction byte IB1 D7 0 offset detection on pin DIAG ...
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... NXP Semiconductors 9.2 Data bytes If R the TDF8599 sends two data bytes to the microprocessor (DB1 and DB2). All short diagnostic and offset protection bits are latched. In addition, all bits are reset after a read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting for all bits is logic 0 ...
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... NXP Semiconductors 10. Limiting values Table 17. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol ORM ESR stg T amb V ESD V (prot) [1] Floating condition assumed for outputs. [2] Current limiting concept. [3] Human Body Model (HBM). [4] Charged-Device Model (CDM). [5] The output pins are defined as the output pins of the filter connected between the TDF8599 output pins and the load ...
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... NXP Semiconductors 12. Static characteristics Table 19. Static characteristics 320 kHz < osc Symbol Parameter Supply V supply voltage P I supply current P I standby current stb I total quiescent current q(tot) Series resistance output switches R drain-source on-state resistance DSon 2 I C-bus interface: pins SCL and SDA ...
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... NXP Semiconductors Table 19. Static characteristics 320 kHz < osc Symbol Parameter SVRR voltage and ACGND input bias voltage in Mute and Operating modes V reference voltage ref Amplifier outputs; pins OUT1N, OUT1P, OUT2N and OUT2P V output offset voltage O(offset) Stabilizer output; pins VSTAB1 and VSTAB2 ...
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... NXP Semiconductors Table 19. Static characteristics 320 kHz < osc Symbol Parameter t delay time d Speaker load impedance R load resistance L [1] Required resistor accuracy for pins ADS and MOD see [2] Maximum leakage current from DCP pin to ground = 3 A. [3] DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode. ...
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... NXP Semiconductors 12.1 Switching characteristics Table 20. Switching characteristics < T < +85 C; unless otherwise specified. P amb Symbol Parameter Internal oscillator f oscillator frequency osc Master/slave setting (OSCIO pin) R oscillator resistance osc V LOW-level output voltage OL V HIGH-level output voltage OH V LOW-level input voltage ...
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... NXP Semiconductors 13. Dynamic characteristics Table 21. Dynamic characteristics kHz specified. Symbol Parameter P output power o THD total harmonic distortion G closed-loop voltage gain v(cl) channel separation cs SVRR supply voltage rejection ratio Z differential input impedance i(dif) V output noise voltage n(o) channel balance bal(ch) ...
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... NXP Semiconductors [ kHz, AES brick wall kHz, AES brick wall, independent 0.5 V RMS. i i(max) 14. Application information 14.1 Output power estimation (Stereo mode) The output power, just before clipping, can be estimated using --------------------------------------------------------------------------------------------------------------------------------------- - Where, • • • R DSon • • t w(min) • ...
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... NXP Semiconductors ( (1) ( THD = 0 0.12 ( C), R DSon 130 ns and I w(min) O(ocp Fig 27 function THD = 0.5 % TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier 001aai796 ( ( 0.025 , (minimum). in stereo mode with Fig 28. P Rev. 02 — 30 July 2009 ...
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... NXP Semiconductors 14.2 Output power estimation (Parallel mode) Figure 29 THD = function of the supply voltage for different load impedances in parallel mode. 160 P o (W) 120 THD = 0 0.06 ( C), R DSon 130 ns and I w(min) O(ocp Fig 29 function THD = 0.5 % 14.3 Output current limiting The peak output current is internally limited maximum. During normal operation, the output current should not exceed this threshold level otherwise the output signal will be distorted ...
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... NXP Semiconductors 14.4 Speaker configuration and impedance A flat-frequency response (due the low-pass filter components (L impedance. Table 22. Load impedance ( ) Remark: When using a 1 after the low-pass filter switches two 2 14.5 Heat sink requirements In some applications necessary to connect an external heat sink to the TDF8599. ...
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... NXP Semiconductors Example 2: • 14 • • T amb • P max • R th(j-a) • T j(max) 14.6 Curves measured in reference design 2 10 THD + N (%) kHz ( 14 kHz ( 14 100 Hz Fig 31. THD + function of output power with a 2 load TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifi ...
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... NXP Semiconductors 1 THD + N (%) Fig 33. THD + function of frequency with a 2 load 60 cs (dB (1) (2) 90 100 14 (1) Channel 1 to channel 2. (2) Channel 2 to channel 1. Fig 35. Channel separation as a function of frequency with a 2 load TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier ...
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... NXP Semiconductors 75 CMRR ( Fig 37. CMRR as a function of frequency 100 (2) (%) ( ( 14 kHz ( 14 kHz Fig 39. Efficiency as a function of output power TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier 001aai806 1.0 G (dB) 0.8 0.6 0.4 0.2 (2) (1) ...
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... NXP Semiconductors 14.7 Typical application schematics V P GND OUT1N 100 100 nF OUT1P OUT2P 100 100 nF OUT2N (1) See (2) See (3) See Fig 41. Example application diagram for dual BTL in non-I TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier bead ...
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... NXP Semiconductors V P GND OUT1N 100 nF 100 nF OUT1P OUT2P 100 nF 100 nF OUT2N (1) See (2) See (3) See Fig 42. Example application diagram for dual BTL in I TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier bead 100 F bead 35 V 100 F ...
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... NXP Semiconductors V P GND OUTN 100 100 nF OUTP (1) See (2) See (3) See Fig 43. Example application diagram for a single BTL in I TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier bead V 100 F bead 100 F bead 1000 F PGND1 35 V PGND2 ...
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... NXP Semiconductors GND (1) See (2) See (3) See (4) See Fig 44. Master-slave example application diagram; dual BTL master and one BTL slave in TDF8599_2 Product data sheet 2 I C-bus controlled dual channel class-D power amplifier bead V P1 100 F bead 100 F bead 1000 F 100 nF PGND1 ...
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... NXP Semiconductors 15. Package outline HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height pin 1 index DIMENSIONS (mm are the original dimensions) A (1) UNIT max 3.5 0.08 0.38 mm 3.5 0.35 3.2 0.04 0.25 Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height pin index DIMENSIONS (mm are the original dimensions) A UNIT max 0.3 3.3 mm 3.6 0.35 0.1 3.0 Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information In accordance with SNW-FQ-611-D. The number of the quality specification can be found in the Quality Reference Handbook. The handbook can be ordered using the code 9398 510 63011. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 47. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 25. Abbreviation BCDMOS BTL DCP EMI LSB M p MSB NDMOST OCP OTP OVP ...
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... NXP Semiconductors 19. Revision history Table 26. Revision history Document ID Release date TDF8599_2 20090730 • Modifications: Data sheet status changed from Objective data sheet to Product data sheet. • Various minor textual inconsistencies in the data sheet corrected. • Changed • Changed • Changed • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 Table 4. I C-bus mode operation . . . . . . . . . . . . . . . . . . .8 2 Table 5. Non-I C-bus mode operation . . . . . . . . . . . . . . .8 Table 6. Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .8 Table 7. Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .11 Table 8. Operation mode selection with the MOD pin . .12 Table 9 ...
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... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3 Pulse-width modulation frequency . . . . . . . . . . 8 8.3.1 Master and slave mode selection . . . . . . . . . . . 8 8 ...