MT47H128M8HQ-187EIT:G Micron Technology Inc, MT47H128M8HQ-187EIT:G Datasheet - Page 65

• Manufacturer Part Number: MT47H128M8HQ-187EIT:G
• Manufacturer: Micron Technology Inc

Specifications of MT47H128M8HQ-187EIT:G

• Lead Free Status / Rohs Status: Compliant

Table 31: DDR2-400/533
All units are shown in picoseconds
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
(V/ns)
Slew
Rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
t
125
4.0 V/ns
DS
83
0
–
–
–
–
–
–
t
DH
45
21
0
–
–
–
–
–
–
t
125
–11
83
Notes:
3.0 V/ns
DS
0
–
–
–
–
–
t
–14
DH
45
21
t
0
–
–
–
–
–
DS,
1. For all input signals, the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be ob-
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 33 (page 67) are the
t
sheet value to the derating value listed in Table 31.
t
crossing of V
signal is defined as the slew rate between the last crossing of V
ing of V
tween the shaded “V
value (see Figure 27 (page 69)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “V
line to the actual signal from the AC level to DC level is used for the derating value (see
Figure 28 (page 69)).
t
crossing of V
signal is defined as the slew rate between the last crossing of V
crossing of V
between the shaded “DC level to V
rating value (see Figure 29 (page 70)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to V
gent line to the actual signal from the DC level to V
value (see Figure 30 (page 70)).
will not have reached V
put signal is still required to complete the transition and reach V
tained by linear interpolation.
characterization.
DQS single-ended slew rate derating with DQS referenced at V
the logic levels
to the AC/DC trip points to DQ referenced to V
Table 36 (page 68). Table 35 provides the V
(
the DQ (
125
–11
–25
t
83
DS nominal slew rate for a rising signal is defined as the slew rate between the last
DH nominal slew rate for a rising signal is defined as the slew rate between the last
t
2.0 V/ns
DS
DH Derating Values with Differential Strobe
0
–
–
–
–
DS
a
and
t
–14
–31
DH
45
21
0
–
–
–
–
IL(AC)max
t
DS
t
DH
a
DQS, DQS# Differential Slew Rate
t
REF(DC)
IL(DC)max
REF(DC)
–13
–31
and
95
12
DS
1.8 V/ns
a
–
1
–
–
–
) for DDR2-533. Table 36 provides the V
t
. If the actual signal is always earlier than the nominal slew rate line be-
DS
t
DH
. If the actual signal is always later than the nominal slew rate line
b
t
–19
–42
and the first crossing of V
DH
33
12
–2
and
–
–
–
–
and the first crossing of V
REF(DC)
a
) for DDR2-400.
IH[AC]
t
DH
t
–19
–43
65
DS
24
13
–1
1.6 V/ns
–
–
–
–
to AC region,” use the nominal slew rate for the derating
b
/V
. Converting the derated base values from DQ referenced
t
DS and
IL[AC]
t
–30
–59
DH
24
10
–7
–
–
–
–
REF(DC)
at the time of the rising clock transition), a valid in-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
REF(DC)
–31
–74
DH required is calculated by adding the data
DS
25
11
–7
1.4 V/ns
–
–
–
–
region,” use the nominal slew rate for the de-
REF
1Gb: x4, x8, x16 DDR2 SDRAM
t
IH(AC)min
–18
–47
–89
to AC region,” the slew rate of a tangent
DH
22
-based fully derated values for the DQ
–
–
–
5
–
REF(DC)
REF
is listed in Table 35 (page 68) and
REF(DC)
–127 –140 –115 –128 –103 –116
Input Slew Rate Derating
t
–19
–62
REF(DC)
23
DS
1.2 V/ns
.
.
–
–
–
–
5
t
t
REF
DH nominal slew rate for a falling
DS nominal slew rate for a falling
-based fully derated values for
region,” the slew rate of a tan-
t
–35
–77
level is used for the derating
DH
17
–6
–
–
–
–
‹ 2007 Micron Technology, Inc. All rights reserved.
REF
REF(DC)
IH(DC)min
t
–50
IH(AC)
DS
17
–7
1.0 V/ns
–
–
–
–
–
and DQ referenced at
/V
and the first cross-
t
–23
–65
DH
IL(AC)
and the first
–
–
–
–
–
6
.
t
–38
DS
0.8 V/ns
5
–
–
–
–
–
–
t
–11
–53
DH
–
–
–
–
–
–