CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet - Page 71

• Manufacturer Part Number: CS4525-CNZ
• Description: IC AMP AUDIO PWR 30W QUAD 48QFN
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZ

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Package / Case: 48-QFN
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 30 W
• Thd Plus Noise: 10 %
• Operating Supply Voltage: 2.5 V to 5 V
• Supply Current: 54 mA
• Maximum Power Dissipation: 180 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio - Load Impedance: 4 Ohms, 6 Ohms, 8 Ohms
• Audio Load Resistance: 8 Ohms, 4 Ohms
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.375 V
• Amplifier Class: D
• No. Of Channels: 4
• Supply Voltage Range: 8V To 18V
• Load Impedance: 4ohm
• Operating Temperature Range: 0°C To +70°C
• Amplifier Case Style: QFN
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1264

DS726PP2
9.2
9.2.1
9.2.2
9.2.3
9.2.4
ADC/SP
7
Input Configuration (Address 02h)
Input Source Selection (ADC/SP)
Default = 0
Function:
This bit selects the audio input source.
ADC High-Pass Filter Enable (EnAnHPF)
Default = 1
Function:
Controls the operation of the ADC high-pass filter.
Serial Port Sample Rate (SPRate[1:0]) - Read Only
Function:
Identifies the sample rate of the incoming LRCK signal on the serial audio input port based on the setting
of the ClkFreq[1:0] bits in Register 01h, the frequency of the internal system clock, and the frequency of
the input LRCK signal.
Input Serial Port Digital Interface Format (DIF [2:0])
Default = 000
Function:
Selects the serial audio interface format used for the data in on SDIN. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options
are detailed in the section
ADC/SP Setting
EnAnHPF Setting
SPRate[1:0] Setting
DIF[2:0] Setting
0 ..........................................Digital input from the serial audio input port.
1 ..........................................Analog input from the internal ADC.
0 ..........................................ADC high-pass filter disabled.
1 ..........................................ADC high-pass filter enabled.
00 ........................................32 kHz
01 ........................................44.1 kHz
10 ........................................48 kHz
11.........................................96 kHz
000 ......................................Left-Justified, up to 24-bit data.
001 ......................................I²S, up to 24-bit data.
010 ......................................Right-Justified, 24-bit data.
011.......................................Right-Justified, 20-bit data.
100 ......................................Right-Justified, 18-bit data.
101 ......................................Right-Justified, 16-bit data.
110.......................................Reserved.
111 .......................................Reserved.
EnAnHPF
6
Reserved
Audio Input Source
ADC High-Pass Filter State
Identified Input Sample Rate
Input Serial Port Serial Audio Interface Format
5
“Serial Audio Interfaces” on page
SPRate1
4
SPRate0
3
62.
DIF2
2
DIF1
1
CS4525
DIF0
0
71