CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet - Page 54

• Manufacturer Part Number: CS4525-CNZ
• Description: IC AMP AUDIO PWR 30W QUAD 48QFN
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZ

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Package / Case: 48-QFN
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 30 W
• Thd Plus Noise: 10 %
• Operating Supply Voltage: 2.5 V to 5 V
• Supply Current: 54 mA
• Maximum Power Dissipation: 180 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio - Load Impedance: 4 Ohms, 6 Ohms, 8 Ohms
• Audio Load Resistance: 8 Ohms, 4 Ohms
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.375 V
• Amplifier Class: D
• No. Of Channels: 4
• Supply Voltage Range: 8V To 18V
• Load Impedance: 4ohm
• Operating Temperature Range: 0°C To +70°C
• Amplifier Case Style: QFN
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1264

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6.2
6.2.1
6.2.2
Hardware Mode
A limited feature set is available when the CS4525 powers up in hardware mode. The available features are
described in the following sections. All device configuration is achieved via hardware control input pins.
6.2.2.1
System Clocking
In hardware mode, the CS4525 must be clocked by a stable external clock source input on the SYS_CLK
pin. This input clock is used to synchronize the input serial audio signals with the internal clock domain
and to clock the internal digital processing, sample-rate converter, and PWM modulators. It is also used
to determine the sample rate of the serial audio input signals in order to automatically configure the vari-
ous internal filter coefficients.
To ensure proper operation, the CS4525 must be informed of the nominal frequency of the supplied
SYS_CLK signal via the ClkFreq[1:0] hardware control pins. These pins must be set to the appropriate
level before the RST signal is released to initiate a power-up sequence. The nominal clock frequencies
indicated by the states of the ClkFreq[1:0] pins are shown in
Specifications
WARNING: The SYS_CLK signal must never be removed or stopped while the RST pin is high and any
of the power output stages are connected to a load. Doing so may result in permanent damage to the
CS4525 and connected transducers.
Figure 22
Power-Up and Power-Down
The CS4525 will remain in a completely powered-down state until the RST pin is brought high.
1. Hold RST low until the power supplies and the input SYS_CLK signal are stable.
2. Bring RST high.
Hardware mode will be entered after approximately 10 ms.
ClkFreq1
High
High
Low
Low
below demonstrates a typical clocking configuration using the SYS_CLK input.
Recommended Power-Up Sequence
table on
Clock
Figure 22. Typical SYS_CLK Input Clocking Configuration
page 23
ClkFreq0
Table 13. SYS_CLOCK Frequency Selection
High
High
Low
Low
for complete input frequency range specifications.
Clock_In
DSP
Reset_Out
Nominal SYS_CLK Frequency
Table 13
RST
27.000 MHz
18.432 MHz
24.576 MHz
below. See the
Reserved
SYS_CLK
CS4525
XTO
XTI
SYS_CLK Switching
CS4525
DS726PP2