SC16IS762IPW-S NXP Semiconductors, SC16IS762IPW-S Datasheet - Page 20

• Manufacturer Part Number: SC16IS762IPW-S
• Description: IC UART DUAL I2C/SPI 28-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of SC16IS762IPW-S

• Features: Low Current
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-2241

Table 10.
Register
address
General register set
0x00
0x00
0x01
0x02
0x02
0x03
0x04
0x05
0x06
0x07
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
SC16IS752/SC16IS762 internal registers
Register
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
TXLVL
RXLVL
IODir
IOState
IOIntEna
reserved
IOControl
EFCR
[5]
[6]
[6]
[7]
[1]
[7]
[3]
[7]
[7]
Bit 7
bit 7
bit 7
CTS interrupt
enable
RX trigger
level (MSB)
FIFO enable
divisor latch
enable
clock
divisor
FIFO data
error
CD
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
reserved
reserved
IrDA mode
(slow/ fast)
[2]
[2]
[3]
[3]
[8]
Bit 6
bit 6
bit 6
RTS interrupt
enable
RX trigger
level (LSB)
FIFO enable
set break
IrDA mode
enable
THR and
TSR empty
RI
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
reserved
reserved
reserved
[2]
[2]
[3]
[3]
[3]
Bit 5
bit 5
bit 5
Xoff
TX trigger
level (MSB)
interrupt
priority bit 4
set parity
Xon Any
THR empty
DSR
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
reserved
reserved
auto RS-485
RTS output
inversion
[2]
[2]
[3]
[3]
[2]
[2]
Bit 4
bit 4
bit 4
Sleep
mode
TX trigger
level (LSB)
interrupt
priority bit 3
even parity
loopback
enable
break
interrupt
CTS
bit 4
bit 4
bit 4
bit 4
bit 4
bit 4
bit 4
bit 4
reserved
reserved
auto RS-485
RTS direction
control
[2]
[3]
[3]
[2]
[2]
Bit 3
bit 3
bit 3
modem status
interrupt
reserved
interrupt
priority bit 2
parity enable
reserved
framing error
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
reserved
UART
software reset
reserved
CD
[3]
[3]
[3]
[3]
Bit 2
bit 2
bit 2
receive line
status
interrupt
TX FIFO
reset
interrupt
priority bit 1
stop bit
TCR and TLR
enable
parity error
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
reserved
I/O[3:0] or
RIB, CDB,
DTRB, DSRB
transmitter
disable
RI
[4]
[2]
[3]
Bit 1
bit 1
bit 1
THR empty
interrupt
RX FIFO
reset
interrupt
priority bit 0
word length
bit 1
RTS
overrun error data in
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
reserved
I/O[7:4] or
RIA, CDA,
DTRA, DSRA
receiver
disable
DSR
[4]
[3]
Bit 0
bit 0
bit 0
RX data
available
interrupt
FIFO enable
interrupt
status
word length
bit 0
DTR (IO5)
receiver
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
reserved
latch
9-bit mode
enable
CTS
[3]
R/W
R
W
R/W
W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W