SC28C94A1A,512 NXP Semiconductors, SC28C94A1A,512 Datasheet - Page 13

• Manufacturer Part Number: SC28C94A1A,512
• Description: IC UART QUAD W/FIFO 52-PLCC
• Manufacturer: NXP Semiconductors
• Type: Quad UARTr

Specifications of SC28C94A1A,512

• Number Of Channels: 4, QUART
• Package / Case: 52-PLCC
• Features: False-start Bit Detection
• Fifo's: 8 Byte
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3993-5; 935262534512; SC28C94A1A; SC28C94A1A

Philips Semiconductors
Vectored Interrupts
The QUART responds to an Interrupt Acknowledge (IACK) initiated
by the host by providing an Interrupt Acknowledge Vector on D7:0.
The interrupt acknowledge cycle is terminated with a DACKN pulse.
The vector provided by the QUART can have one of the three forms
under control of the IVC control field (bits 1:0 of the Interrupt Control
Register):
With IVC = 00 (IVR only)
With IVC = 01 (channel number)
With IVC = 10 (type & channel number)
Table 4.
MR0 (Mode Register 0)
MR1 (Mode Register 1)
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
NOTE: Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
CSR (Clock Select Register)
CR (Command Register)
NOTE: Issuing commands contained in the upper four bits of the “Command Register” should be separated in time by at least three (3) X1
clock edges. Allow four (4) edges if the “X1 clock divide by 2” mode is used. A disabled transmitter cannot be loaded.
2006 Aug 09
Bit 7
0 = No
1 = Yes
00 = Normal
01 = Auto-echo
10 = Local loop
11 = Remote loop
Rx Watchdog
Quad universal asynchronous receiver/transmitter (QUART)
Control
RxRTS
Timer
0 = off
1 = on
Channel Mode
IVR7:5
3
Register Bit Formats, Duart ab. [duplicated for Duart cd]
Bit 6
Normally set to 0
RxINT1 Select
IVR7:2
RxINT2 bit
Miscellaneous Commands
6
Receiver Clock Select
These bits should normally be set to 0
IVR7:0
See text
See text
8
Bit 5
0 = Char
1 = Block
0 = No
1 = Yes
Type
Error Mode*
3
Control
TxRTS
TxINT Control
Bit 4
00 = With parity
01 = Force parity
10 = No parity
11 = Wake-up mode
0 = No
1 = Yes
CTS Enable Tx
Chan #
Chan #
2
2
SD00163
Parity Mode
13
0 = No
1 = Yes
Bit 3
0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
1 = 0.625 5 = 0.875 9 = 1.625 C = 1.875
2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
Disable Tx
A code of 11 in the Interrupt Vector Control Field of the ICR results
in NO interrupt vector being generated. The external data bus is
driven to a high impedance throughout the IACK cycle. A DACKN
will be generated normally for the IACK cycle, however.
NOTE: If IACKN is not being used then the command “UPDATE
CIR” must be issued for the global and interrupt registers to be
updated.
PROGRAMMING UART CONTROL REGISTERS
The operation of the QUART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the CPU.
Addressing of the registers is described in Table 1.
The bit formats of the QUART registers are depicted in Table 2.
x
They should be considered Reserved.
0 = No
1 = Yes
Bit 2
0 = Even
1 = Odd
These bits not implemented.
Parity Type
Enable Tx
Transmitter Clock Select
x
Stop Bit Length*
See text
0 = No
1 = Yes
Bit 1
Disable Rx
00 = 5
01 = 6
10 = 7
11 = 8
x
Bits per Character
SC28C94
Product data sheet
0 = No
1 = Yes
Bit 0
Enable Rx
x