SCC2681TC1A44,518 NXP Semiconductors, SCC2681TC1A44,518 Datasheet - Page 9
![IC DUART SOT187-2](/photos/6/98/69845/568-44-plcc_sot187-2_sml.jpg)
SCC2681TC1A44,518
Manufacturer Part Number
SCC2681TC1A44,518
Description
IC DUART SOT187-2
Manufacturer
NXP Semiconductors
Datasheet
1.SCC2681TC1A44518.pdf
(15 pages)
Specifications of SCC2681TC1A44,518
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
3Bit
Voltage - Supply
4.5 V ~ 5.5 V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935274519518
SCC2681TC1A44-T
SCC2681TC1A44-T
SCC2681TC1A44-T
SCC2681TC1A44-T
5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
4. Test conditions for outputs: C
7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
8. Minimum frequencies are not tested but are guaranteed by design.
Philips Semiconductors
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
and the signal negated first terminates the cycle.
be negated for t
RDN input even if the CEN is used as the strobing signal for bus operations.
(WRITE)
(WRITE)
(READ)
(READ)
A0–A3
D0–D7
D0–D7
WRN
RDN
CEN
CEN
EHEL
t
AVEL
FLOAT
to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
t
RLDA
L
= 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C
RESET
t
ELAX
t
RLDV
t
WLWH
INVALID
t
RLRH
t
DVWH
VALID
Figure 3. Reset Timing
Figure 4. Bus Timing
t
RES
VALID
9
t
WHDI
t
t
EHEL
RHDI
t
RHDF
SD00028
t
EHEL
L
= 50 pF, R
FLOAT
L
= 2.7 k to V
SCC2681T
SD00100
Product data
CC
.