SC16C2552BIA44,512 NXP Semiconductors, SC16C2552BIA44,512 Datasheet - Page 17

• Manufacturer Part Number: SC16C2552BIA44,512
• Description: IC UART DUAL SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552BIA44,512

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274408512; SC16C2552BIA44; SC16C2552BIA44

NXP Semiconductors
SC16C2552B_3
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits and the parity are selected by writing the
appropriate bits in this register.
Table 12.
Table 13.
Table 14.
Table 15.
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[1:0] word length
LCR[4]
X
0
1
0
1
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 03 — 12 February 2009
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
LCR[3]
0
1
1
1
1
Word length (bits)
5
6
7
8
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Stop bit length (bit times)
1
1
2
1
2
Table
Table
15).
Table
14).
13)
SC16C2552B
© NXP B.V. 2009. All rights reserved.
17 of 38