SC16C852SVIET,157 NXP Semiconductors, SC16C852SVIET,157 Datasheet - Page 38

• Manufacturer Part Number: SC16C852SVIET,157
• Description: IC UART DL 1.8V W/FIFO 36-TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852SVIET,157

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286451157; SC16C852SVIET; SC16C852SVIET

NXP Semiconductors
10. Dynamic characteristics
Table 38.
T
[1]
[2]
[3]
SC16C852SV_1
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
XTAL1
d(CS-LLA)
su(A-LLAL)
w(LLA)
h(LLAH-A)
d(IOW)
d(IOR-DV)
w(IOR)
d(LLAH-IORL)
w(IOW)
h(IOWH-D)
d(LLAH-IOWL)
su(D-IOWH)
d(IOR)
dis(IOR-QZ)
d(IOW-Q)
d(modem-INT)
d(IOR-INTL)
WH
WL
w(clk)
d(stop-INT)
d(start-INT)
d(IOW-TX)
d(IOW-INTL)
w(RESET_N)
amb
External clock only; maximum crystal frequency is 24 MHz.
10 % of the data bus fall or rise time.
RCLK is an internal frequency and it is equal to the sampling rate times the baud rate.
= 40 C to +85 C; V
Dynamic characteristics
Parameter
frequency on pin XTAL1
delay time from CS to LLA
set-up time from address to LLA LOW
LLA pulse width time
address hold time after LLA HIGH
IOW delay time
delay time from IOR to data valid
IOR pulse width time
delay time from LLA HIGH to IOR LOW
IOW pulse width time
data input hold time after IOW HIGH
delay time from LLA HIGH to IOW LOW
set-up time from data input to IOW HIGH
IOR delay time
disable time from IOR to high-impedance
data output
delay time from IOW to data output
delay time from modem to INT
delay time from IOR to INT LOW
pulse width HIGH
pulse width LOW
clock pulse width
delay time from stop to INT
delay time from start to INT
delay time from IOW to TX
delay time from IOW to INT LOW
pulse width on pin RESET
DD
[2]
= 1.65 V to 1.95 V; unless otherwise specified.
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 01 — 23 September 2008
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
[1]
[3]
[3]
Min
-
10
5
10
10
10
-
28
10
10
5
10
5
10
-
-
-
-
6
6
12.5
-
-
8T
-
10
RCLK
SC16C852SV
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2008. All rights reserved.
Max
80
-
-
-
-
-
40
-
-
-
-
-
-
-
20
50
50
50
-
-
-
1T
1T
24T
50
-
RCLK
RCLK
RCLK
38 of 48
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
ns
ns