SC68C752BIBS,157 NXP Semiconductors, SC68C752BIBS,157 Datasheet - Page 8

• Manufacturer Part Number: SC68C752BIBS,157
• Description: IC UART DUAL 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIBS,157

• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280969157; SC68C752BIBS; SC68C752BIBS

NXP Semiconductors
SC68C752B_4
Product data sheet
Fig 4.
Fig 5.
D7 to D0
Auto flow control (auto-RTS and auto-CTS) example
N = receiver FIFO trigger level.
The two blocks in dashed lines cover the case where an additional byte is sent, as described in
RTSn functional timing
RTSn
RXn
R/W
6.2.1 Auto-RTS
TRANSMIT
RECEIVE
Start
If both auto-CTS and auto-RTS are enabled, when RTSn is connected to CTSn, data
transmission does not occur unless the receive FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
Auto-RTS data flow control originates in the receiver block (see
of SC68C752B” on page
trigger levels used in auto-RTS are stored in the TCR. RTSn is active if the receiver FIFO
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is
reached, RTSn is de-asserted. The sending device (for example, another UART) may
send an additional byte after the trigger level is reached (assuming the sending UART has
another byte to send) because it may not recognize the de-assertion of RTSn until it has
begun sending the additional byte. RTSn is automatically reasserted once the receiver
FIFO reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows
the sending device to resume transmission.
FIFO
FIFO
UART 1
byte N
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
Stop
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
RTSn
CTSn
RXn
Start
TXn
3).
Figure 5
byte N + 1
1
shows RTSn functional timing. The receiver FIFO
TXn
CTSn
RXn
RTSn
2
Stop
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
N
TRANSMIT
RECEIVE
FIFO
FIFO
Section
Figure 1 “Block diagram
SC68C752B
N + 1
6.2.1.
002aaf090
002aab086
© NXP B.V. 2010. All rights reserved.
Start
D7 to D0
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