MAX3110ECWI+G36 Maxim Integrated Products, MAX3110ECWI+G36 Datasheet - Page 16
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MAX3110ECWI+G36
Manufacturer Part Number
MAX3110ECWI+G36
Description
IC UART/TXRX RS232 W/CAPS 28SOIC
Manufacturer
Maxim Integrated Products
Type
SPI/MICROWIRE-Compatible UART with Integrated ESD-Protected RS-232 Transceiverr
Datasheet
1.MAX3110ECWIG36.pdf
(31 pages)
Specifications of MAX3110ECWI+G36
Features
Transceiver
Number Of Channels
1, UART
Protocol
RS232, RS485
Voltage - Supply
4.5 V ~ 5.5 V
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)
Data Rate
250 Kbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Supply Current
0.6 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Description/function
SPI/MICROWIRE-Compatible UART with integrated ESD-protected RS-232 transceiver
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Propagation Delay Time Ns
150 ns
No. Of Channels
1
Uart Features
SPI/QSPI/MICROWIRE-Compatible µC Interface, Internal Charge-Pump Capacitors
Supply Voltage Range
4.5V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Notes:
bit 15: DOUT
R = 1, Data is available to be read or is being read from the
receive register or FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bits 13–0: DOUT
Zeros
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 2. Write Configuration (D15, D14 = 1, 1)
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
16
DOUT
DIN
BIT
______________________________________________________________________________________
15
R
1
14
1
T
FEN
13
0
SHDNi
12
0
TM
11
0
RM
10
0
PM
9
0
RAM
8
0
bits 15, 14: DIN
1,1 = Write Configuration
bit 13: DIN
FEN = 0, FIFO is enabled.
FEN = 1, FIFO is disabled.
bit 12: DIN
SHDNi = 1, Enter software shutdown.
SHDNi = 0, Exit software shutdown.
bit 11: DIN
TM = 1, Transmit buffer empty interrupt is enabled.
TM = 0, Transmit buffer empty interrupt is disabled.
bit 10: DIN
RM = 1, Data available in the receive register or FIFO interrupt
is enabled.
RM = 0, Data available in the receive register or FIFO interrupt
is disabled.
bit 9: DIN
PM = 1, Parity bit high received interrupt is enabled.
PM = 0, Parity bit received interrupt is disabled.
bit 8: DIN
RAM = 1, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
RAM = 0, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
bit 7: DIN
IR = 1, IrDA mode is enabled.
IR = 0, IrDA mode is disabled.
bit 6: DIN
ST = 1, Transmit two stop-bits.
ST = 0, Transmit one stop-bit.
bit 5: DIN
PE = 1, Parity is enabled for both transmit (state of Pt) and
receive.
PE = 0, Parity is disabled for both transmit and receive.
bit 4: DIN
L = 1, 7-bit words (8-bit words if PE = 1)
L = 0, 8-bit words (9-bit words if PE = 1)
bits 3–0: DIN
B3–B0 = XXXX, Baud-Rate Divisor Select Bits (see Table 6)
IR
7
0
ST
6
0
PE
5
0
4
L
0
B3
3
0
B2
2
0
B1
1
0
B0
0
0